2006
DOI: 10.1109/ted.2006.885663
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At-Bias Extraction of Access Parasitic Resistances in AlGaN/GaN HEMTs: Impact on Device Linearity and Channel Electron Velocity

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Cited by 59 publications
(28 citation statements)
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“…As shown in Figure 70, r s at high current levels is more than 3 times larger than under low current conditions. This result has been confirmed by DiSanto et al (2006) after extracting the source access resistance from small-signal s-parameter measurements as shown in Figure 71. This increase in r s must be taken into account for an accurate extraction of the intrinsic performance of AlGaN/GaN HEMTs.…”
Section: Effect Of Access Resistances In Device Linearitysupporting
confidence: 60%
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“…As shown in Figure 70, r s at high current levels is more than 3 times larger than under low current conditions. This result has been confirmed by DiSanto et al (2006) after extracting the source access resistance from small-signal s-parameter measurements as shown in Figure 71. This increase in r s must be taken into account for an accurate extraction of the intrinsic performance of AlGaN/GaN HEMTs.…”
Section: Effect Of Access Resistances In Device Linearitysupporting
confidence: 60%
“…Recently, Ridley et al (2004) have suggested the electron scattering with the nonequilibrium hot phonon population as a possible reason to explain the decrease in g m and f T in AlGaN/GaN HEMTs, and remains an area of active research. Access resistances have also been proposed as a major reason responsible for the degradation of device linearity with bias (Palacios et al, 2005;Disanto, 2006). As analyzed in detail in Section 5.06.4.1.1, the decrease of g m (and f T ) at high currents can be explained by the increase of the small-signal source access resistance, r s , with drain current without invoking hot phonon scattering (Figures 70 and 71).…”
Section: Gain Linearity With Drain Currentmentioning
confidence: 98%
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“…However, measuring these parasitics on individual FETs is not a straightforward task. The estimation is typically tackled either by numerical optimization or analytical manipulation of smallsignal models [29], [30] or by relying on bias conditions that are quite far from operating conditions (e.g., the end-resistance technique [31] and its variants [32]). A disadvantage of the former approach is that it is difficult to attach a clear physical meaning to the extracted resistance values; on the other hand, the latter approach measures R S and R D under bias conditions where the current flow is very far from normal.…”
mentioning
confidence: 99%
“…The extracted terminal inductances are similarly well behaved. The present extraction procedure is more robust than that of [12], because the fitting is performed over the entire frequency range without having to shunt out the gate contact. Parasitic capacitances are extracted from test structures that are fabricated on the semi-insulating substrate directly.…”
Section: A Extrinsic Model Elementsmentioning
confidence: 99%