Asynchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz

Schuster, S.E.; Reohr, W.; Cook, Peter W.; Heidel, D.; Immediato, M.; Jenkins, K.A.

doi:10.1109/isscc.2000.839786

Cited by 48 publications

(28 citation statements)

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“…RGD-arbiter asP*, RGD arbiter in [20] described at transistor level. IPCMOS A pulse-based controller for asynchronous pipelines in [21]. STARI A self-timed pipeline in [22].…”

Section: Resultsmentioning

confidence: 99%

Efficient Hybrid Reachability Analysis for Asynchronous Concurrent Systems

Pastor¹,

Peña²

2003

Lecture Notes in Computer Science

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Abstract. Symbolic reachability analysis based on Binary Decision Diagrams (BDDs) is a technique that allows the implementation of efficient state space exploration algorithms. However, in practice it is well known that the BDD blowup problem limits the size of the systems that can be analyzed. Conversely, simulation is a low-cost state generation technique, although its effectiveness is limited due to its inherent sequentiality. We present a hybrid methodology that combines simulation and symbolic traversal in order to improve the state space exploration of large systems. The methodology concentrates on asynchronous concurrent systems, whose peculiarities are not fully exploited by other existing techniques for hybrid verification. Our approach exploits the information obtained from simulations to improve the knowledge of the state space, effectively guiding symbolic traversal. We demonstrate the applicability of this methodology in the verification of complex control-dominated asynchronous circuits.

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“…RGD-arbiter asP*, RGD arbiter in [20] described at transistor level. IPCMOS A pulse-based controller for asynchronous pipelines in [21]. STARI A self-timed pipeline in [22].…”

Section: Resultsmentioning

confidence: 99%

Efficient Hybrid Reachability Analysis for Asynchronous Concurrent Systems

Pastor¹,

Peña²

2003

Lecture Notes in Computer Science

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“…or mixed implementation tends to abandon the classical single-clock framework in favor of a multiclock one, each clock controlling a circuit zone or a local processor. A good example of this is described in [12], where a single global clock was abandonned for a design style with multiple local clocks. Communication between clock zones becomes a critical issue and is carefully controlled either by inserting special devices such as latches or by fine timing analysis.…”

Section: Introductionmentioning

confidence: 99%

Multiclock Esterel

Berry¹,

Sentovich²

2001

Lecture Notes in Computer Science

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Abstract. We present the Multiclock Esterel language, which extends the synchronous language Esterel to multiple clock zones. While Esterel is good for compact single-clocked hardware or software designs, modern electronic designs are growing rapidly and they can no longer be designed in a monolithic fashion. Problems such as clock distribution, complexity, and power limitations have led designers to construct designs in a modular, multiple clock fashion. Multiclock Esterel is designed precisely to address this design style. It is a natural extension of Esterel, and retains its strong synchronous semantics and internal determinism. Statements driven by different clocks communicate through two special devices called the sampler and the reclocker. Multiclock Esterel should be understood as a preliminary language proposal meant to study multiclocking. It has not yet been validated by large experiments.

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“…This could be viewed as a coarser scale version of standard bundled data design, where a unique delay is used to match the worst case path in each of many small combinational logic blocks. Design styles with even more localised delay assumptions include IPCMOS [12] which uses a pulse generator to strobe latches, and GASP with self-reset [15].…”

Section: Reviewmentioning

confidence: 99%