Asynchronous 8-bit processor mapped into an FPGA device

Herrera, Moises; Viveros, Francisco

doi:10.1109/colcomcon.2014.6860430

Cited by 4 publications

(2 citation statements)

References 16 publications

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“…Before the earlier design, 6 to 10 ASICs, required and all the modules are assembled together and communicates through a common data path [15]. 8 bit RISC processor is mapped into FPGA, described in Verilog or HDL having simple 8 bit arithmetic and logic unit is presented in [16], and implemented using SPARTAN-6. As there is increment in speed, power decreases and increase in maximum computability.…”

Section: Introductionmentioning

confidence: 99%

Architectural Enhancement of Processor with 8 Bit Multiplier and 16 Bit Co-operative ALU using VHDL

Dudhane¹

2020

IJETER

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In the new world of science and technology with the tremendous changes in electronic gadgets such as microprocessors and microcontrollers, becoming an important blocks of the electronics industry. For any processor, CPU has integral part which is ALU, responsible for the efficient work of the processor. This paper integrates the computing ability of 8 bit processor with 16 bit cooperative arithmetic and logic unit and 8by8 bit multiplication. In this technology, 8 bit processor keeps its ability with excellent input/ output control with maintaining its simple architecture and low power consumption. FPGA offers a platform for designing and implementing soft cores for improvement in execution time and developing IP cores. 16F84 RISC processor is designed module wise developed with HDL language and implemented using FPGA with enhanced architecture. The results are obtained in three ways as firstly designing and implementing 16 bit CALU with 8 bit processor, secondly 8by8 bit multiplier and thirdly combined integration of 16 bit CALU and 8by8 bit multiplier. Simulation result for 8 bit multiplier shows execution time of 109.241 ns, with 16 bit CALU is 674.66 ns and with multiplier and 16 bit CALU is 583.33 ns, 76.09 % cycle saving is achieved with the implementation using reconfigurable hardware, improving execution time from 674.66 ns to 583.33 ns. The design is configured on Xilinx 14.6 using FPGA and implemented using Verilog or HDL.

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Section: Introductionmentioning

confidence: 99%

Architectural Enhancement of Processor with 8 Bit Multiplier and 16 Bit Co-operative ALU using VHDL

Dudhane¹

2020

IJETER

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“…On the other hand, these architectures can be implemented according to the distribution of memory: they can be Harvard (Trivedi and Tripathi 2015) or Von Newman (Pastor and Sánchez 1997). The RISC processors have been implemented as Design and Performance Analysis of 8-bit RISC Processor using Xilinx Tool (Uma 2012), designing a low power 8-bit Application Specific Processor (Samal and Samal 2014), and FPGA Implementation of MIPS RISC Processor (Kelgaonkar and Kodgire n.d.), FPGA Implementation of an 8-bit Simple Processor (Ayeh et al 2008), Asynchronous 8-Bit Processor Mapped into an FPGA Device (Herrera and Viveros 2014). Regarding CISC processors, the design of an 8-bit CISC CPU based on FPGA has diferentes fabricantes, de tal forma que el usuario solo tenga que definir los puertos de entada y de salida, según el FPGA utilizado.…”

Section: Introductionmentioning

confidence: 99%

8-bit softcore microprocessor with dual accumulator designed to be used in FPGA

Santa

Rodríguez²,

Sánchez³

2018

tecnura

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Context: This paper is presents the design and implementation of an 8-bit softcore RISC microprocessor able to be run on space-optimized FPGA, in order to be used for embedded applications. Method: The design of this microprocessor was developed in Verilog hardware description language and can be implemented in FPGA from different manufacturers; therefore, the user has only to define the input and output ports according to the type of FPGA. This is an accumulator-type processor, but it has two different accumulators that can be used as pointers for indirect addressing. The processor is Harvard with a RAM of 8x256 bits, and a ROM that can be resized from 17x252 bits to 17x8K bits. Additionally, it has one 8-bit input port, one 8-bit output port, and one 8-bit address port, which means that the processor can address more than 256 8-bit output and input ports/devices. Results: The developed processor, named "ZA-SUA," was compared with PICOBLAZE softcore and other three similar processors of free distribution in the Web, and some improvements over those were found. Criteria such as the Flip Flops used, occupied LUTs, Slices in use, and maximum delay of each processor were analyzed, all these results were obtained from the implementation of the processors in the Xilinx FPGAs. Conclusions: The designed architecture is composed by two accumulators, which can be used either as source or destination for the operation of the ALU. This fact gives some flexibility to the design, doing it better than a single-accumulator processor, and getting it closer to the register-based processors.

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Simple method of asynchronous circuits implementation in commercial FPGAs

Hajduk

2017

Integration

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Asynchronous 8-bit processor mapped into an FPGA device

Cited by 4 publications

References 16 publications

Architectural Enhancement of Processor with 8 Bit Multiplier and 16 Bit Co-operative ALU using VHDL

Architectural Enhancement of Processor with 8 Bit Multiplier and 16 Bit Co-operative ALU using VHDL

8-bit softcore microprocessor with dual accumulator designed to be used in FPGA

Simple method of asynchronous circuits implementation in commercial FPGAs

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