Asynchronous 2-Phase Level-Encoded Convention Logic (LCL)

Tran, Linh Duc; Pham, Thanh V.; Kavehei, Omid; Matthews, Glenn I.

doi:10.1109/isee2.2019.8921032

Cited by 6 publications

(5 citation statements)

References 11 publications

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“…NCL utilizes multi-rail logic, most commonly the dual-rail logic, to eliminate timing references, and a 4-phased handshaking-protocol for synchronization and control. A 2phase protocol could also serve as an alternative handshaking scheme [16]. Unlike Boolean logic, dual-rail encoding requires two wires per variable to represent one bit of information (i.e., logic '0' or '1'), thus simultaneously representing both literals of the variable.…”

Section: Ncl Backgroundmentioning

confidence: 99%

Evolution of NULL Convention Logic Based Asynchronous Paradigm: An Overview and Outlook

Khodosevych

Sakib

2022

IEEE Access

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The synchronous design paradigm dominates today's semiconductor industry. However, this clocked approach is facing major challenges with today's high-speed, low-power design expectations, using processes with ever-increasing physical level variability. Several clock related issues surface in designs operating at higher frequencies, which make clock management increasingly difficult. Quasi-delay insensitive (QDI) asynchronous (clockless) designs have proved to be effective in circumventing the major limiting factors associated with the clocked designs. NULL Convention Logic (NCL) is one such QDI asynchronous design paradigm, which presents itself as a promising alternative to conventional synchronous circuits and has already found numerous commercial applications due to its low power, robust architecture, and ease of design reuse. This paper presents the evolution of NCL based asynchronous paradigm over the past two decades, primarily focusing on existing fundamental research in NCL design automation, spanning over NCL synthesis, optimization, testing, and verification. The methods are systematically analyzed to determine their limitations and future research directions.

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Section: Ncl Backgroundmentioning

confidence: 99%

Evolution of NULL Convention Logic Based Asynchronous Paradigm: An Overview and Outlook

Khodosevych

Sakib

2022

IEEE Access

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“…Asynchronous NOCs based on 2-phase LEDR is projected as an efficient solution as it provides better performance compared to 4 phase encoding in terms of power and throughput, but 2-phase signal handling needs complex design [2]. In this paper, we are proposing simple yet efficient LEDR encoder and decoder circuits.…”

Section: Proposed Designmentioning

confidence: 99%

“…(1) Though asynchronous designs proved efficient over synchronous counterparts in terms of scalability, power consumption, and better timing constraints. But they have some severe drawbacks when area and speed are considered due to complex handshake control circuits which increase the static power loss [2]. In this study, we offer a proposal for a highspeed, low-power small NOC architecture based on LEDR encoding and a lightweight router…”

Section: Introductionmentioning

confidence: 99%

A Minimal Buffer Router with Level Encoded Dual Rail-Based Design of Network-on-Chip Architecture

Patil

Sandi

Raj

et al. 2022

Wireless Communications and Mobile Computing

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Asynchronous NOCs are most prominent in present SOC designs, due to their low dynamic power consumption, modularity, heterogeneous nature, and robustness to the process variations. Though asynchronous designs are proved efficient over synchronous counterparts, they have some severe drawbacks when area and speed are considered, due to complex handshake control circuits which increase the static power loss. Quasidelay insensitive (QDI) class of asynchronous NOCs based on 2-phase encoding is proved beneficial for speed and throughput enhancement but with complex design. The work has introduced lightweight minimal buffer router based on LEDR encoding to design a low power, high speed with compact NOC architecture. Then, minimal buffer router with FSM-based arbiter and priority assigner block is designed to enhance the speed, power, and area. This proposed work achieves zero dynamic power consumption with a total power consumption of less than 0.082 W with a router latency of 0.8 ns.

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“…Ongoing work aims to develop backend flows to support different QDI templates, e.g. SDDS-Velo [12], LCL [13] and others. Another limitation of Pulsar is its lack of formal verification, relying mostly in post-synthesis simulation for validation.…”

Section: Conclusion and Ongoing Workmentioning

confidence: 99%

A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow

Sartori

Moreira

Calazans

2020

2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)

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Asynchronous quasi-delay-insensitive circuits are known for their robustness against variations, but their widespread use has been prey to the absence of adequate design methods and lack of design and verification tools. The recently proposed Pulsar flow enables the design and optimisation of quasi-delay-insensitive circuits using conventional EDA tools, enhanced by adequate libraries, methods and models. Pulsar enables designers to naturally trade performance for power or area, whenever there is slack in timing budgets. However, Pulsar lacked an automated dual-rail expansion method to support its operation, requiring that designers manually develop a timing model as input to the computation of asynchronous cycle time constraints. This paper proposes and describes the features of a frontend for Pulsar. Pulsar-F, the new flow version can be used as a push-button design tool for asynchronous QDI circuits. Pulsar-F adds the following features to Pulsar: (i) an RTL-based design capture method; (ii) a heuristic, timing-driven singlerail pre-synthesis process using commercial EDA tools; (iii) a dual-rail expansion technique with fine-grain acknowledgement network generation; (iv) a tool that automates the computation of the Hal-Buffer Channel Network (HBCN) graph-based timing model for pre-synthesised circuits and derives a set of timing constraints for it. Experiments show that Pulsar-F improves Pulsar to further aid asynchronous designers to trade off power, area and performance.

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Asynchronous 2-Phase Level-Encoded Convention Logic (LCL)

Cited by 6 publications

References 11 publications

Evolution of NULL Convention Logic Based Asynchronous Paradigm: An Overview and Outlook

Evolution of NULL Convention Logic Based Asynchronous Paradigm: An Overview and Outlook

A Minimal Buffer Router with Level Encoded Dual Rail-Based Design of Network-on-Chip Architecture

A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow

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