A Minimal Buffer Router with Level Encoded Dual Rail-Based Design of Network-on-Chip Architecture

Abstract

Asynchronous NOCs are most prominent in present SOC designs, due to their low dynamic power consumption, modularity, heterogeneous nature, and robustness to the process variations. Though asynchronous designs are proved efficient over synchronous counterparts, they have some severe drawbacks when area and speed are considered, due to complex handshake control circuits which increase the static power loss. Quasidelay insensitive (QDI) class of asynchronous NOCs based on 2-phase encoding is proved beneficial for speed and throughput enhancement but with complex design. The work has introduced lightweight minimal buffer router based on LEDR encoding to design a low power, high speed with compact NOC architecture. Then, minimal buffer router with FSM-based arbiter and priority assigner block is designed to enhance the speed, power, and area. This proposed work achieves zero dynamic power consumption with a total power consumption of less than 0.082 W with a router latency of 0.8 ns.

2D router chip design, analysis, and simulation for effective communication

“…Additionally, compared to other routing protocols, it is much easier to create and implement different routing protocols into it. Therefore, crossbar architecture has been created in VHDL and simulated in Xilinx ISE 14.1 to use the Xilinx XC5VLX30-3 FPGA to evaluate the operation of NoC on hardware [17]. Routers are based on the wormhole switching principle.…”