Asymmetric Energy Distribution of Interface Traps in n- and p-MOSFETs With&amp;lt;tex&amp;gt;$hbox HfO _2$&amp;lt;/tex&amp;gt;Gate Dielectric on Ultrathin SiON Buffer Layer

Han, Jin‐Ping; Vogel, Eric M.; Gusev, Evgeni; D'Emic, C.; Richter, Curt A.; Heh, D.; Suehle, John S.

doi:10.1109/led.2004.824247

Cited by 41 publications

(23 citation statements)

References 12 publications

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“…The interface trap density (D it ) obtained from subthreshold characteristic does not indicate a clear trend. Nevertheless, an opposite trend for trap distribution has been reported recently [21,22] and this discrepancy might be attributed to different process-related parameters. It should be noted that the dielectric trap density (N t ) here is the average effective values for the multi-interfaced dielectric stack considered.…”

Section: Resultsmentioning

confidence: 79%

Improved low frequency noise characteristics of sub-micron MOSFETs with TaSiN/TiN gate on ALD HfO2 dielectric

Devireddy

Min

Çelik‐Butler

et al. 2007

Microelectronics Reliability

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Section: Resultsmentioning

confidence: 79%

Improved low frequency noise characteristics of sub-micron MOSFETs with TaSiN/TiN gate on ALD HfO2 dielectric

Devireddy

Min

Çelik‐Butler

et al. 2007

Microelectronics Reliability

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“…This endurance degradation is attributed to the interface-trap generation and the electron trapping in the tunneling oxide [15,16]. In order to verify the endurance degradation, a charge pumping method was employed [17,18]. Here, the charge pumping current (I cp ) measurements were carried out as follows: A square pulse was applied to the gate of the selected SONOS cell while the source and substrate were grounded.…”

Section: Resultsmentioning

confidence: 99%

Investigation of Endurance Degradation in a CTF NOR Array Using Charge Pumping Methods

Kim²

2016

Transactions on Electrical and Electronic Materials

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The NOR-type SONOS memory devices used in this study were fabricated using a standard 0.35 μm complementary-metaloxide-semiconductor (CMOS) technology. In these devices, the We investigate the effect of interface states on the endurance of a charge trap flash (CTF) NOR array using charge pumping methods. The endurance test was completed from one cell selected randomly from 128 bit cells, where the memory window value after 10 2 program/erase (P/E) cycles decreased slightly from 2.2 V to 1.7 V. However, the memory window closure abruptly accelerated after 10 3 P/E cycles or more (i.e. 0.97 V or 0.7 V) due to a degraded programming speed. On the other hand, the interface trap density (Nit) gradually increased from 3.13×10 11 cm -2 for the initial state to 4×10 12 cm -2 for 10 2 P/E cycles. Over 10 3 P/E cycles, the Nit increased dramatically from 5.51×10 12 cm -2 for 10 3 P/E cycles to 5.79×10 12 cm -2 for 10 4 P/E cycles due to tunnel oxide damages. These results show good correlation between the interface traps and endurance degradation of CTF devices in actual flash cell arrays. Ho-Myoung An

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“…It clearly suggests that the stiction can generate the interface traps or oxide traps in the suspended structures because the SS and V Hys are largely influenced by those traps [10,12,13,14]. Furthermore, the NW-SUS-STC show larger fluctuations in its electrical parameters ( Fig.…”

Section: Device Fabricationmentioning

confidence: 98%

Electrical and pH sensing characteristics of Si nanowire-based suspended FET biosensors

Kım

Park

Rim

et al. 2014

14th IEEE International Conference on Nanotechnology

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The dependence of nanowire width on the stiction-free structure and the influence of stiction on the electrical performance in the suspended nanowire (NW-SUS) ion-sensitive field-effect transistors (ISFETs) are investigated. The NW-SUS ISFETs without stiction are successfully fabricated using advanced microfabrication technology. The stiction-free NW-SUS ISFETs exhibit excellent electrical characteristics due to gate-all-around (GAA) structure. Furthermore, the stiction-free NW-SUS ISFETs show higher sensitivity in pH sensing, compared to the conventional devices. These investigations provide an opportunity for developing sensor platform with high sensitivity in the future.

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Asymmetric Energy Distribution of Interface Traps in n- and p-MOSFETs With<tex>$hbox HfO _2$</tex>Gate Dielectric on Ultrathin SiON Buffer Layer

Cited by 41 publications

References 12 publications

Improved low frequency noise characteristics of sub-micron MOSFETs with TaSiN/TiN gate on ALD HfO2 dielectric

Improved low frequency noise characteristics of sub-micron MOSFETs with TaSiN/TiN gate on ALD HfO2 dielectric

Investigation of Endurance Degradation in a CTF NOR Array Using Charge Pumping Methods

Electrical and pH sensing characteristics of Si nanowire-based suspended FET biosensors

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