Associative processors and memories: a survey

Grosspietsch, K.E.

doi:10.1109/40.141599

Cited by 66 publications

(20 citation statements)

References 23 publications

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“…Match-line sense amplifiers detect whether ML has a match or a miss condition. Finally, the encoder maps the matching location to its matching address [10] (more references here). CAM compares input search data against a table of stored data and returns the address of the matching data.…”

Section: How Cam Workmentioning

confidence: 99%

Proposal for the development of 3D Vertically Integrated Pattern Recognition Associative Memory (VIPRAM)

Deptuch¹,

Hoff²,

Kwan³

et al. 2010

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Executive SummaryFuture particle physics experiments looking for rare processes will have no choice but to address the demanding challenges of fast pattern recognition in triggering as detector hit density becomes significantly higher due to the high luminosity required to produce the rare process. We propose to develop a 3D Vertically Integrated Pattern Recognition Associative Memory (VIPRAM) chip for HEP applications, to advance the state-of-the-art for pattern recognition and track reconstruction for fast triggering.3D technology is the integration of thinned and bonded silicon integrated circuits with vertical interconnects between IC layers using through silicon vias (TSVs). The technology has wide applications in industry, ranging from memories to pixel arrays to microprocessors and FPGAs. Performance can be improved significantly by reducing interconnect R/L/C for higher speed and density. In addition, it provides the freedom to divide functionality among tiers to create new designs that are simply not possible in 2D. As Moore's law is approaching severe limitations, it is expected that 3D technology will be the next scaling engine. Generally speaking, 3D technology becomes useful when a task can be partitioned into multiple sections that are physically and logically separable, and the interconnections among them are straightforward. Moreover, the use of 3D technology can have varied goals. For example, it can be used to increase transistor density -i.e. to increase the number of transistors per square micron. Such is a major goal of 3D DRAM design. Here, the DRAM task is first logically divided into a control/interface section and memory core. The control/interface section is physically separated onto its own tier, and the memory core is further divided into memory banks which are each vertically integrated onto their own tiers. A second, different example is the 3D integration of microprocessor systems. Here, different functions that have been traditionally separated can be brought together in a single monolithic structure and technological limitations can be eliminated. CPU and memory can be placed on separate tiers and the interconnect between them -i.e. the memory bus -can be reduced from on the order of tens of millimeters (a bus on a PC board) to a few tens of microns (the length of a through silicon via). Also, the memory bus itself can be expanded from a few bits to hundreds of bits wide, dramatically improving the memory access bandwidth.With Pattern Recognition Associative Memory for HEP tracking trigger applications, the task is indeed logically and physically dividable and the interconnections among them are straightforward, making it a good candidate for 3D integration. Associative Memories, in HEP, are based on the concept of a Content Addressable Memory (CAM) -memory that is not accessed by providing the memory cell with an appropriate address, but rather a memory that is accessed by providing the memory cell with some related content. In the case of tracking triggers in HEP, that content ...

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Section: How Cam Workmentioning

confidence: 99%

Proposal for the development of 3D Vertically Integrated Pattern Recognition Associative Memory (VIPRAM)

Deptuch¹,

Hoff²,

Kwan³

et al. 2010

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“…Match-line sense amplifiers detect whether each ML has a match or a miss condition. Finally, the encoder maps the matching location to its matching address [15] [16]. A CAM compares input search data against a table of stored data and returns the address of the matching data.…”

Section: How Cam Work and 3d Advantages For Prammentioning

confidence: 99%

Developement of 3D Vertically Integrated Pattern Recognition Associative Memory (VIPRAM)

Deputch¹,

Shochet²,

Lipton³

et al. 2011

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“…CAM [14][15][16][17][18] is a storage array designed to find the location of a particular stored value by comparing the input against all of the values in the storage array simultaneously in 1-clock cycle. In binary CAMs, data comprises only from "1" or "0", while in ternary CAMs (TCAM), data comprises from "1", "0", or " * " (do not care) bits.…”

Section: Content Addressable Memorymentioning

confidence: 99%

Packet Classification by Multilevel Cutting of the Classification Space: An Algorithmic‐Architectural Solution for IP Packet Classification in Next Generation Networks

Aldiab

Garcia-Palacios

Crookes

et al. 2008

Journal of Computer Networks and Communications

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Recommended by Maode MaTraditionally, the Internet provides only a "best-effort" service, treating all packets going to the same destination equally. However, providing differentiated services for different users based on their quality requirements is increasingly becoming a demanding issue. For this, routers need to have the capability to distinguish and isolate traffic belonging to different flows. This ability to determine the flow each packet belongs to is called packet classification. Technology vendors are reluctant to support algorithmic solutions for classification due to their nondeterministic performance. Although content addressable memories (CAMs) are favoured by technology vendors due to their deterministic high-lookup rates, they suffer from the problems of high-power consumption and high-silicon cost. This paper provides a new algorithmic-architectural solution for packet classification that mixes CAMs with algorithms based on multilevel cutting of the classification space into smaller spaces. The provided solution utilizes the geometrical distribution of rules in the classification space. It provides the deterministic performance of CAMs, support for dynamic updates, and added flexibility for system designers.

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Associative processors and memories: a survey

Cited by 66 publications

References 23 publications

Proposal for the development of 3D Vertically Integrated Pattern Recognition Associative Memory (VIPRAM)

Proposal for the development of 3D Vertically Integrated Pattern Recognition Associative Memory (VIPRAM)

Developement of 3D Vertically Integrated Pattern Recognition Associative Memory (VIPRAM)

Packet Classification by Multilevel Cutting of the Classification Space: An Algorithmic‐Architectural Solution for IP Packet Classification in Next Generation Networks

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