Associative Instruction Reordering to Alleviate Register Pressure

Rawat, Poonam; Sukumaran-Rajam, Aravind; Rountev, Atanas; Rastello, Fabrice; Pouchet, Louis-Noël; Sadayappan, P.

doi:10.1109/sc.2018.00049

Cited by 11 publications

(6 citation statements)

References 25 publications

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“…The baseline performance is on-par to (and often exceeds) state-of-the-art GPUoptimized stencil codes reporting the highest performance across different stencil benchmarks. Namely, SSAM [5], register-optimized stencils [59], [60], StencilGen [40], and temporal blocking AN5D [4].…”

Section: B Benchmarks and Datasets 1) Stencil Benchmarksmentioning

confidence: 99%

Persistent Kernels for Iterative Memory-bound GPU Applications

Zhang¹,

Wahib²,

Chen³

et al. 2022

Preprint

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Iterative memory-bound solvers commonly occur in HPC codes. Typical GPU implementations have a loop on the host side that invokes the GPU kernel as much as time/algorithm steps there are. The termination of each kernel implicitly acts as the barrier required after advancing the solution every time step. We propose a scheme for running memory-bound iterative GPU kernels: PERsistent KernelS (PERKS). In this scheme the time loop is moved inside a persistent kernel, and device-wide barriers are used for synchronization. We then reduce the traffic to device memory by caching a subset of the output in each time step in registers and shared memory to be used as input for the following time step. PERKS can be generalized to any iterative solver: they are largely independent of the solver's implementation. We explain the design principle of PERKS and demonstrate the effectiveness of PERKS for a wide range of iterative 2D/3D stencil benchmarks (geometric mean speedup of 2.29x in small domains and 1.53x in large domains), and a Krylov subspace solver (geometric mean speedup of 4.67x in smaller SpMV datasets from SuiteSparse and 1.39x in larger SpMV datasets, for conjugate gradient).

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Section: B Benchmarks and Datasets 1) Stencil Benchmarksmentioning

confidence: 99%

Persistent Kernels for Iterative Memory-bound GPU Applications

Zhang¹,

Wahib²,

Chen³

et al. 2022

Preprint

View full text Add to dashboard Cite

show abstract

“…Data reuse has also been extensively recognized and exploited. Prior work [33,34,39,54] on optimizing the order of execution instructions could decrease loads/stores operations to relieve the register pressure, while only the individual element in each vector could be reused. Basu designs a vector code generation scheme to reuse several vectors in the computation process, and it is constrained to constantcoefficient and isotropic stencils [6].…”

Section: Related Workmentioning

confidence: 99%

“…The first one is based on the associativity of the weighted sums of neighboring points. Specifically, the execution order of one stencil computation can be rearranged to exploit common subexpressions or data reuse at register or cache level [6,12,33,34,54]. Consequently, the number of load/store operations can be reduced and the bandwidth usage is alleviated in optimized execution order.…”

Section: Introductionmentioning

confidence: 99%

Reducing Redundancy in Data Organization and Arithmetic Calculation for Stencil Computations

Li¹,

Yuan²,

Zhang³

et al. 2021

Preprint

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Stencil computation is one of the most important kernels in various scientific and engineering applications. A variety of work has focused on vectorization techniques, aiming at exploiting the in-core data parallelism. Briefly, they either incur data alignment conflicts or hurt the data locality when integrated with tiling. In this paper, a novel transpose layout is devised to preserve the data locality for tiling in the data space and reduce the data reorganization overhead for vectorization simultaneously. We then propose an approach of temporal computation folding designed to further reduce the redundancy of arithmetic calculations by exploiting the register reuse, alleviating the increased register pressure, and deducing generalization with a linear regression model. Experimental results on the AVX-2 and AVX-512 CPUs show that our approach obtains a competitive performance.

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“…Register allocation is generally considered a practically solved problem [15]. For most applications, the register allocation strategy in the production compiler is very effective in controlling the number of loads/stores and register overflows.…”

Section: Instruction Reorderingmentioning

confidence: 99%

On the Transformation Optimization for Stencil Computation

Zhang

Mei

2021

Electronics

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Stencil computation optimizations have been investigated quite a lot, and various approaches have been proposed. Loop transformation is a vital kind of optimization in modern production compilers and has proved successful employment within compilers. In this paper, we combine the two aspects to study the potential benefits some common transformation recipes may have for stencils. The recipes consist of loop unrolling, loop fusion, address precalculation, redundancy elimination, instruction reordering, load balance, and a forward and backward update algorithm named semi-stencil. Experimental evaluations of diverse stencil kernels, including 1D, 2D, and 3D computation patterns, on two typical ARM and Intel platforms, demonstrate the respective effects of the transformation recipes. An average speedup of 1.65× is obtained, and the best is 1.88× for the single transformation recipes we analyze. The compound recipes demonstrate a maximum speedup of 1.92×.

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Associative Instruction Reordering to Alleviate Register Pressure

Cited by 11 publications

References 25 publications

Persistent Kernels for Iterative Memory-bound GPU Applications

Persistent Kernels for Iterative Memory-bound GPU Applications

Reducing Redundancy in Data Organization and Arithmetic Calculation for Stencil Computations

On the Transformation Optimization for Stencil Computation

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