Assessing the Role of Program Suspend Operation in 3D NAND Flash Based Solid State Drives

Abstract

3D NAND Flash is the preferred storage medium for dense mass storage applications, including Solid State Drives and multimedia cards. Improving the latency of these systems is a mandatory task to narrow the gap between computing elements, such as CPUs and GPUs, and the storage environment. To this extent, relatively time-consuming operations in the storage media, such as data programming and data erasing, need to be prioritized and be potentially suspendable by shorter operations, like data reading, in order to improve the overall system quality of service. However, such benefits are strongly dependent on the storage characteristics and on the timing of the single operations. In this work, we investigate, through an extensive characterization, the impacts of suspending the data programming operation in a 3D NAND Flash device. System-level simulations proved that such operations must be carefully characterized before exercising them on Solid State Drives to eventually understand the performance benefits introduced and to disclose all the potential shortcomings.

EXPRESS: Exploiting Energy–Accuracy Tradeoffs in 3D NAND Flash Memory for Energy-Efficient Storage

“…dicating that the NAND array is busy for the duration of the program operation, The 𝑡 𝑝𝑟𝑜𝑔 value lies in the range of 300-600 μs for an SLC memory page of the chip in this study [27]. The program operation, however, can be terminated prematurely a RESET command, such as the program suspend operation [28]. In this case, the st the RB pin is illustrated with the red dashed line.…”

High-Density Solid-State Memory Devices and Technologies

“…The first research paper in the Special Issue is by Zambelli et al [7] and investigates the benefits and shortcomings of program suspend operations in 3D NAND Flash Solid-State Drives. Through experimental analyses and system-level simulations, the impact of including program suspend in the command set of the storage device on its speed, reliability and power consumption is clarified.…”

A Novel Program Suspend Scheme for Improving the Reliability of 3D NAND Flash Memory

“…Previously reported works [8,9] studied the timing and sequence of the program suspend and resume scheme in NAND flash memory chip, where methods to reduce the required response time between program suspend command and read command were proposed. Progressively, one recent work [10] assessed the role of program suspend scheme in 3D NAND flash memory in SSD systems level, and suggested that the program suspend operation must be characterized carefully prior to its usage, to achieve better performance. In fact, in order to ensure the reliability of NAND device, the program suspend scheme in NAND chip must be carefully optimized when program suspend command is issued.…”

“…Correspondingly, this work first studies the conventional program suspend scheme [9] in section II. Next, two series of experiments are designed to measure the read fail bit count (FBC) [10]- [12] when program suspend and resume operations execute, since read FBC is one of the key parameters to characterize the reliability of the memory. It is found that read FBC increases significantly if program suspend command is issued in the program stage when the delay time between the program suspend operation and other operations exceeds tens of milliseconds.…”