ASIC implementation of a unified hardware architecture for non-key based cryptographic hash primitives

Ganesh, T.S.; Sudarshan, T. S. B.

doi:10.1109/itcc.2005.91

Cited by 7 publications

(6 citation statements)

References 9 publications

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“…In Table 1, the work of [12] is a unified solution for MD5, SHA1 and RIPEMD160 so that the gate count is quite large. [13] used 0.13µm technology but it is much slower than our proposal which used [17] has a small cycle number and a large gate area due to the unfolding transformation with a large unfolding factor of 8.…”

Section: Synthesis Results and Comparisonmentioning

confidence: 99%

See 1 more Smart Citation

Design Methodology for Throughput Optimum Architectures of Hash Algorithms of the MD4-class

Lee

Chan

Verbauwhede

2008

J Sign Process Syst Sign Image Video Technol

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Abstract. In this paper we propose an architecture design methodology to optimize the throughput of MD4-based hash algorithms. The proposed methodology includes an iteration bound analysis of hash algorithms, which is the theoretical delay limit, and DFG (Data Flow Graph) transformations to achieve the iteration bound. We applied the methodology to some MD4-based hash algorithms such as SHA1, MD5 and RIPEMD-160. Since SHA1 is the algorithm which requires all the techniques we show, we also synthesized the transformed SHA1 algorithm in a 0.18µm CMOS technology in order to verify its correctness and its achievement of high throughput. To the best of our knowledge, the proposed SHA1 architecture is the first to achieve the theoretical throughput optimum beating all previously published results. Though we demonstrate a limited number of examples, this design methodology can be applied to any other MD4-based hash algorithm.

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Section: Synthesis Results and Comparisonmentioning

confidence: 99%

“…Many of the published papers combine multiple techniques to achieve a higher throughput. SHA1 is implemented in [7,[10][11][12][13][14], SHA2 is implemented in [4,5,[8][9][10]13], MD5 is implemented in [12][13][14][15][16] and RIPEMD-160 is implemented in [12,13,15].…”

Section: Related Workmentioning

confidence: 99%

Design Methodology for Throughput Optimum Architectures of Hash Algorithms of the MD4-class

Lee

Chan

Verbauwhede

2008

J Sign Process Syst Sign Image Video Technol

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show abstract

“…While there exist several papers that analyze the combination of different block ciphers and hash functions (mostly combining MD5 with SHA-1, e.g., [24,25,26,27]), there exists only one publication that focuses on the combination of AES and Grøstl on FPGA platforms. Järvinen [28] analyzed various resource-sharing techniques to reduce the area requirements for an Altera Cyclone III.…”

Section: Related Workmentioning

confidence: 99%

Putting together What Fits together - GrÆStl

Pelnar

Muehlberghuber

Hutter

2013

Smart Card Research and Advanced Applications

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Abstract. We present GrAEStl, a combined hardware architecture for the Advanced Encryption Standard (AES) and Grøstl, one of the final round candidates of the SHA-3 hash competition. GrAEStl has been designed for low-resource devices implementing AES-128 (encryption and decryption) as well as Grøstl-256 (tweaked version). We applied several resource-sharing optimizations and based our design on an 8/16-bit datapath. As a feature, we aim for high flexibility by targeting both ASIC and FPGA platforms and do not include technology or platform-dependent components such as RAM macros, DSPs, or Block RAMs. Our ASIC implementation (fabricated in a 0.18 µm CMOS process) needs only 16.5 kGEs and requires 742/1,025 clock cycles for encryption/decryption and 3,093 clock cycles for hashing one message block. On a Xilinx Spartan-3 FPGA, our design requires 956 logic slices and 302 logic slices on a Xilinx Virtex-6. Both stand-alone implementations of AES and Grøstl outperform existing FPGA solutions regarding low-area design by needing 79 % and 50 % less resources as compared to existing work. GrAEStl is the first combined AES and Grøstl implementation that has been fabricated as an ASIC.

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“…Many of the published papers combine multiple techniques to achieve a higher throughput. SHA1 is implemented in [35,31,36,20,42,45], SHA2 in [12,13,33,11,31,42], MD5 in [20,42,45,37,25] and RIPEMD-160 in [20,42,37,27].…”

Section: Common Techniques Used For Efficient Hardware Implementationmentioning

confidence: 99%

Hardware design for Hash functions

Lee

Knežević

Verbauwhede

2009

Integrated Circuits and Systems

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ASIC implementation of a unified hardware architecture for non-key based cryptographic hash primitives

Cited by 7 publications

References 9 publications

Design Methodology for Throughput Optimum Architectures of Hash Algorithms of the MD4-class

Design Methodology for Throughput Optimum Architectures of Hash Algorithms of the MD4-class

Putting together What Fits together - GrÆStl

Hardware design for Hash functions

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