ASIC design of digital ECG filter

Abstract

In this paper an ASIC design of digital linear phase ECG filter is presented. The filter is utilizing a novel recursive multiplierless architecture. A bit-serial approach has been chosen to keep circuit area and power consumption as small as possible. The implementation has been done using partly full custom and partly standard cell techniques yielding high transistor density and gate array design eficiency. In the implementation module generators have been used to allow flexible altering of the filter structure.