Architecture and circuit design for DSP-ASIC

Vainio, Olli; Tenhunen, Hannu; Nurmi, Jari

doi:10.1109/easic.1990.207910

Cited by 4 publications

(1 citation statement)

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“…The decimator subsequently can manage the incoming data in one of two ways: bit-serial or bit-parallel. The bit-parallel design is used in high performance applications where high speed is required and power is not a large concern [5]. A bit-serial design offers the low power that the bit-parallel design lacks, but it will often be slower, requiring a decreased sampling speed and more time to process data.…”

Section: Bit-serial V Bit-parallel Systemsmentioning

confidence: 99%

A Low Power 15-Bit Decimator in 0.18um CMOS for Biomedical Applications

Scholfield

2013

2013 Euromicro Conference on Digital System Design

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Biomedical devices are often battery operated and require low power consumption. As biomedical devices increase in complexity to include multiple functions such as signal processing and data storage, the constraint on power consumption becomes a larger issue. This paper presents a low power design for a decimator as part of a sigma-delta ADC for biomedical application in a commercial 0.18Pm CMOS process. To make the design low power, it makes use of a bit-serial architecture, a low supply voltage of 0.9V and a clock rate of 1MHz.

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Section: Bit-serial V Bit-parallel Systemsmentioning

confidence: 99%