Array placement for storage size reduction in embedded multimedia systems

Greef, Eddy De; Catthoor, Francky; Man, H. De

doi:10.1109/asap.1997.606813

Cited by 38 publications

(45 citation statements)

References 18 publications

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“…This condition is checked line 6, by comparing 1.0 (the edge density of a clique) with the edge density of the subgraph of G formed by the remaining vertices in C. To this purpose nb edge , the number of edges of this subgraph, is decremented line 9 by the number of edges in E linking the removed vertex v * to vertices in C. Lines 10 to 12, the costs of the remaining vertices are updated for the next iteration. -Clique maximization (lines [14][15][16][17][18][19]: This last part of the algorithm ensures that the clique C is maximal by adding neighbor vertices to it. To become a member of the clique, a vertex must be adjacent to all its members.…”

Section: Methods 3 To Compute a Lower Bound -Heuristic For The Maximummentioning

confidence: 99%

“…Indeed, the identification of the "memory wall" problem in 1995 [35] revealed memory issues as a major concern for developers of embedded systems. Memory issues strongly impact the quality and performance of an embedded system, as the area occupied by the memory can be as large as 80% of a chip and may be responsible for a major part of its power consumption [35,14]. Despite the large silicon area allocated to memory banks, the amount of internal memory available on most embedded Multiprocessor Systems-on-Chips (MPSoCs) is still limited.…”

Section: Introductionmentioning

confidence: 99%

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Memory Analysis and Optimized Allocation of Dataflow Applications on Shared-Memory MPSoCs

Desnos

Pelcat

Nezan

et al. 2014

J Sign Process Syst

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The majority of applications, ranging from the low complexity to very multifaceted entities requiring dedicated hardware accelerators, are very well suited for Multiprocessor Systems-on-Chips (MPSoCs). It is critical to understand the general characteristics of a given embedded application: its behavior and its requirements in terms of MPSoC resources.This paper presents a complete method to study the important aspect of memory characteristic of an application. This method spans the theoretical, architectureindependent memory characterization to the quasi optimal static memory allocation of an application on a real shared-memory MPSoC. The application is modeled as an Synchronous Dataflow (SDF) graph which is used to derive a Memory Exclusion Graph (MEG) essential for the analysis and allocation techniques. Practical considerations, such as cache coherence and memory broadcasting, are extensively treated.Memory footprint optimization is demonstrated using the example of a stereo matching algorithm from the computer vision domain. Experimental results show a reduction of the memory footprint by up to 43% compared to a state-of-the-art minimization technique, a throughput improvement of 33% over dynamic allocation, and the introduction of a tradeoff between multicore scheduling flexibility and memory footprint.

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Section: Methods 3 To Compute a Lower Bound -Heuristic For The Maximummentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Memory Analysis and Optimized Allocation of Dataflow Applications on Shared-Memory MPSoCs

Desnos

Pelcat

Nezan

et al. 2014

J Sign Process Syst

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show abstract

“…Our technique of characterizing the times at which tokens are written and read differs from the lifetimebased approach used by many HLL compilers [18,19], SDF compilers [6], and high level synthesis tools [20,21]. Briefly, the lifetime-based approaches try to determine the first time the token is written (buffer start time) and the time it is read (buffer stop time).…”

Section: Related Workmentioning

confidence: 99%

“…We have shown [7] that modeling the lifetimes of individual tokens in a multirate SDF graph can have prohibitive complexity that would preclude polynomial time solutions. Indeed, the algorithms that DeGreef et al present have a worst case complexity that is exponential in the size of the input program [21]. Informally, the worst case exponential complexity arises in our dataflow model because the number of tokens that have to be allocated is exponential in the size of the input dataflow specification, and it is not clear whether it would be possible to somehow model all of the tokens implicitly, using a structure of size polynomial in the size of the SDF graph, while still retaining the ability to exploit the differing lifetimes of each token.…”

Section: Related Workmentioning

confidence: 99%

“…The overlaying possibility that we expose through the CBP parameter could also be achieved using lifetime analysis techniques and graph coloring. This is the approach taken by DeGreef, Catthoor, and De Man [21] where they have developed lifetime analysis and memory allocation techniques for single-assignment, static control-flow specifications that involve explicit looping constructs, such as for loops [21], in a synthesis tool called ATOMIUM. While we cannot directly compare our approach with that of DeGreef because of differences in the starting specification used (we use a restricted subset of dataflow while they use a single-assignment static control-flow language), there are certain parallels we can draw.…”

Section: Related Workmentioning

confidence: 99%

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The CBP Parameter: A Module Characterization Approach for DSP Software Optimization

Bhattacharyya

Murthy

2004

The Journal of VLSI Signal Processing-Systems for Signal, Image

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Abstract. Memory consumption is an important metric for DSP software implementation. In this paper, we develop a module characterization technique that promotes more economical use of memory resources at the system level. Our work is developed in the context of software synthesis from signal/video/image processing applications expressed as synchronous dataflow (SDF) graphs. SDF is a restricted form of dataflow where each computational module (actor) consumes and produces a fixed number of data values (tokens) on each execution. Usually, no assumption is made about when during the execution of an actor, the tokens are actually consumed and produced; the firing of an actor is treated as an atomic event for most purposes. However, we show in this paper that it is possible to concisely and precisely capture key properties pertaining to the relative times at which tokens are produced and consumed by an actor. We show this by introducing the consumed-before-produced (CBP) parameter, which provides a general method for characterizing the token transfer of an SDF actor. Good bounds on the CBP parameter can aid an SDF compiler in performing more aggressive optimizations for reducing buffer sizes on the edges between actors. We formally define the CBP parameter; derive some useful properties of this parameter; illustrate how the value of the parameter is derived by examining in detail the multirate FIR filter, which is a fundamental actor in multirate signal processing applications; and examine CBP parameterizations for several other practical SDF actors.

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Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC

Han

Chae²,

Brisolara³

et al. 2007

Des Autom Embed Syst

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Emerging embedded systems require heterogeneous multiprocessor SoC architectures that can satisfy both high-performance and programmability. However, as the complexity of embedded systems increases, software programming on an increasing number of multiprocessors faces several critical problems, such as multithreaded code generation, heterogeneous architecture adaptation, short design time, and low cost implementation. In this paper, we present a software code generation flow based on Simulink to address these problems. We propose a functional modeling style to capture data-intensive and controldependent target applications, and a system architecture modeling style to seamlessly transform the functional model into the target architecture. Both models are described using Simulink. From a system architecture Simulink model, a code generator produces a multithreaded code, inserting thread and communication primitives to abstract the heterogeneity of the target architecture. In addition, the multithread code generator called LESCEA applies the extensions of dataflow based memory optimization techniques, considering both data and control dependency. Experimental results on a Motion-JPEG decoder and an H.264 decoder show that the proposed multithread code generator enables easy software programming on different multiprocessor architectures with substantially reduced data memory size (up to 68.0%) and code memory size (up to 15.9%).

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Array placement for storage size reduction in embedded multimedia systems

Cited by 38 publications

References 18 publications

Memory Analysis and Optimized Allocation of Dataflow Applications on Shared-Memory MPSoCs

Memory Analysis and Optimized Allocation of Dataflow Applications on Shared-Memory MPSoCs

The CBP Parameter: A Module Characterization Approach for DSP Software Optimization

Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC

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