2009 IEEE International Symposium on Circuits and Systems 2009
DOI: 10.1109/iscas.2009.5118184
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Arithmetic/logic blocks for fine-grained reconfigurable units

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Cited by 6 publications
(2 citation statements)
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“…In the applications where computational complexity and time consuming are important constraints, it is possible to implement alternative algorithms with comparable performance but lesser complexity than Pan & Tompkins algorithm. A further improvement for algorithm performance can be obtained using a different hardware approach, based, for example, on hardware accelerators as shown in [22], [23], [24], [25], [26], [27] and [28].…”
Section: Discussionmentioning
confidence: 99%
“…In the applications where computational complexity and time consuming are important constraints, it is possible to implement alternative algorithms with comparable performance but lesser complexity than Pan & Tompkins algorithm. A further improvement for algorithm performance can be obtained using a different hardware approach, based, for example, on hardware accelerators as shown in [22], [23], [24], [25], [26], [27] and [28].…”
Section: Discussionmentioning
confidence: 99%
“…To face these constraints in [1], [2] the authors proposed a new architecture named ADAPTO in the which LUTs [5] used for the implementation of general purpose logic have been replaced by Full-Adders (FAs). The resulting architecture is less expensive with respect to those proposed in the literature, but this favorable characteristic is counterbalanced by a reduced flexibility.…”
Section: Introductionmentioning
confidence: 99%