Area-time-power efficient VLSI design for residue-to-binary converter based on moduli set (2&lt;sup&gt;n&lt;/sup&gt;,2&lt;sup&gt;n+1&lt;/sup&gt;&amp;#x2212;1,2&lt;sup&gt;n&lt;/sup&gt;&amp;#x2212;1)

Lin, Su-Hon; Sheu, Ming‐Hwa; Wang, Chao-Hsiang; Kuo, Yuan-Ching

doi:10.1109/apccas.2008.4745987

Cited by 1 publication

(4 citation statements)

References 6 publications

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“…Mapping from the RNS system to integers, Z, is performed by Chinese reminder theorem (CRT) [34][35][36]. The CRT states that binary/decimal representation of a number can be obtained from its RNS through Eq.…”

Section: Residue Number System (Rns)mentioning

confidence: 99%

“…We assume that this interval is sufficient to map the input values, which does not exceeds ± 2. Thirdly, the reverse converter unit is simple and regular [36] because it does not employ any memory.…”

Section: Residue Number System (Rns)mentioning

confidence: 99%

“…However, the moduli set P n = {2 n − 1, 2 n , 2 n+1 − 1} can be efficiently implemented by four modulo adders and two multiplexers (step 6 from Fig. 3) [36]. Figure 6 shows the block diagram of the RBC of P 7 , which is adapted from [36].…”

Section: The Reverse Convertermentioning

confidence: 99%

“…3) [36]. Figure 6 shows the block diagram of the RBC of P 7 , which is adapted from [36]. The output of the RBC is unsigned (3 * n + 1)-bit integer number.…”

Section: The Reverse Convertermentioning

confidence: 99%

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An optimized two-level discrete wavelet implementation using residue number system

Alzaq

Ustundag

2018

EURASIP J. Adv. Signal Process.

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Using discrete wavelet transform (DWT) in high-speed signal processing applications imposes a high degree of caution to hardware resource availability, latency and power consumption. In this paper, we investigated the design and implementation aspects of a multiplier-free two-level DWT by using residue number system (RNS). The proposed two-level takes the advantage of performing the multiplication operations using only the memory without involving special multiplier units, which preserves valuable resources for other critical tasks within the FPGA. The design was implemented and synthesized in ZYNQ ZC706 development kit, taking advantage of embedded block RAMs (BRAMs). The results of the overall experimentations showed that there is a considerable improve in the proposed two-level DWT design with regard to latency and peak signal-to-noise ratio (PSNR) precision value in the final output.

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Section: Residue Number System (Rns)mentioning

confidence: 99%

Section: Residue Number System (Rns)mentioning

confidence: 99%

Section: The Reverse Convertermentioning

confidence: 99%

“…3) [36]. Figure 6 shows the block diagram of the RBC of P 7 , which is adapted from [36]. The output of the RBC is unsigned (3 * n + 1)-bit integer number.…”

Section: The Reverse Convertermentioning

confidence: 99%

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