Area, power and temperature optimization during binary decision diagram based circuit synthesis

Das, Apangshu; Debnath, Akash; Pradhan, Sambhu Nath

doi:10.1109/devic.2017.8074058

Cited by 1 publication

(2 citation statements)

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“…In this paper, an attempt is made to limit excessive temperature growth by reducing the Pd of a circuit and attempting to keep the peak temperature of a circuit within the restricted operating temperature range. 20 The SROBDD is utilized to limit the Pd, and a rapid converging multi-objective search algorithm called nondominated sorting genetic algorithm-II (NSGA-II) is used to identify the best variable ordering. To the best of our knowledge, NSGA-II algorithm is not used in this study to obtain the variable reordering.…”

Section: Introductionmentioning

confidence: 99%

“…where “ T chip ” signifies average chip temperature, “ T amb ” denotes ambient temperature (typical CPU ambient temperature is,

T_{a m b} = 4 5^{\circ}

C), “ R th ” denotes corresponding thermal resistance of silicon substrate and heat sink (constant for a particular element), “total_power” reflects total power consumption, and “total_Area” reflects chip area. In this paper, an attempt is made to limit excessive temperature growth by reducing the Pd of a circuit and attempting to keep the peak temperature of a circuit within the restricted operating temperature range 20 . The SROBDD is utilized to limit the Pd, and a rapid converging multi‐objective search algorithm called nondominated sorting genetic algorithm‐II (NSGA‐II) is used to identify the best variable ordering.…”

Section: Introductionmentioning

confidence: 99%

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Shared reduced ordered binary decision diagram‐based thermal‐aware network synthesis

Das

Singh

Pradhan

2022

Circuit Theory & Apps

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Summary In this work, a multi‐objective algorithm based on nondominated sorting genetic algorithm‐II (NSGA‐II) for thermal‐aware realization of a combinational logic network has been implemented. Input variable ordering of shared reduced ordered binary decision diagram (SROBDD) is done using NSGA‐II such that resulting combinational circuit generates low hotspots by suitable power density distribution. Simultaneous co‐optimization among area, power, and temperature is important in the higher levels of electronic circuit design to reduce the cooling cost. Using a multi‐objective algorithm (NSGA‐II), an effort is made to decrease the temperature by co‐optimization between the power density, area, and power simultaneously. Microelectronics Center of North Carolina (MCNC) benchmark circuits are tested using the proposed approach and an improvement of 13.65% in the silicon area and up to 10% in power dissipation, and 2.72% peak temperature reduction is reported in comparison to existing literature. HotSpot tool and Cadence Innovus are used to determine the peak temperature, actual silicon chip area, and power dissipation of algorithmic optimized solutions.

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Section: Introductionmentioning

confidence: 99%

“…where “ T chip ” signifies average chip temperature, “ T amb ” denotes ambient temperature (typical CPU ambient temperature is,

T_{a m b} = 4 5^{\circ}

Section: Introductionmentioning

confidence: 99%

Shared reduced ordered binary decision diagram‐based thermal‐aware network synthesis

Das

Singh

Pradhan

2022

Circuit Theory & Apps

Self Cite

View full text Add to dashboard Cite

show abstract

Area, power and temperature optimization during binary decision diagram based circuit synthesis

Cited by 1 publication

References 15 publications

Shared reduced ordered binary decision diagram‐based thermal‐aware network synthesis

Shared reduced ordered binary decision diagram‐based thermal‐aware network synthesis

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