Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators

CAxCNN: Towards the Use of Canonic Sign Digit Based Approximation for Hardware-Friendly Convolutional Neural Networks

“…It can be observed that while DRUM [34] provides a latency that is comparable with φ x = 3, the error incurred is much higher. Similarly, φ x = 2 representation results in a multiplier design that has lower latency and error (MAE, MAPE) as compared to Mult8x8Cc [35] and logMultK_w [36]. The area requirement of the multipliers that are designed for the proposed CA x representation is also lower as compared to the approximate multipliers being evaluated.…”

“…For DRUM [34], a configuration of DRUM (8,4) was utilized. For [35], the Mult8x8Cc implementation was used that consists of a combination of 4x2 and 4x4 approximate multipliers along with approximate addition. For [36] the online implementation of logMultK_w with w = 5 was utilized.…”

Hybrid binary-unary truncated multiplication for DSP Applications on FPGAs

“…Note that the accurate multipliers do not present any errors beyond the quantization error of truncating the final output. We consider the truncated quantized output to be the gold standard 1 . The last column of the table shows the ratio between the area of the proposed multipliers to those of the Xilinx LogiCORE IP.…”

“…Although these multipliers can provide high performance, there are some limitations that might affect their usage and degrade the overall performance for some applications. Ullah et al in [1] showed that the fixed location of hard multipliers results in decreasing the routing resource utilization and increasing the critical path delay of some DSP applications. Furthermore, these dedicated multipliers have been optimized to implement the non-truncated, multiplication of two -bit numbers which yields a 2 -bit product.…”

“…By randomly selecting multipliers from [10], the authors in [11] showed that ASIC-based approximate designs offer minimal savings when they are ported to FPGA platforms. Ullah et al in [1] exploited the FPGA fabric and proposed approximate 4 × 2 and 4 × 4 multipliers as basic blocks for designing higher-order multipliers. The authors in [12] presented the "Ap-proxFPGAs" methodology that uses machine learning models to find pseudo-pareto-optimal approximate circuits for FPGA-based designs using the state-of-the-art ASIC-based approximate circuits.…”