Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders

Abstract

This article presents two area/latency optimized gate level asynchronous full adder designs which correspond to early output logic. The proposed full adders are constructed using the delay-insensitive dual-rail code and adhere to the four-phase return-to-zero handshaking. For an asynchronous ripple carry adder (RCA) constructed using the proposed early output full adders, the relative-timing assumption becomes necessary and the inherent advantages of the relative-timed RCA are: (1) computation with valid inputs, i.e., forward latency is data-dependent, and (2) computation with spacer inputs involves a bare minimum constant reverse latency of just one full adder delay, thus resulting in the optimal cycle time. With respect to different 32-bit RCA implementations, and in comparison with the optimized strong-indication, weak-indication, and early output full adder designs, one of the proposed early output full adders achieves respective reductions in latency by 67.8, 12.3 and 6.1 %, while the other proposed early output full adder achieves corresponding reductions in area by 32.6, 24.6 and 6.9 %, with practically no power penalty. Further, the proposed early output full adders based asynchronous RCAs enable minimum reductions in cycle time by 83.4, 15, and 8.8 % when considering carry-propagation over the entire RCA width of 32-bits, and maximum reductions in cycle time by 97.5, 27.4, and 22.4 % for the consideration of a typical carry chain length of 4 full adder stages, when compared to the least of the cycle time estimates of various strong-indication, weak-indication, and early output asynchronous RCAs of similar size. All the asynchronous full adders and RCAs were realized using standard cells in a semi-custom design fashion based on a 32/28 nm CMOS process technology.

Sense Amplifier Half Buffer Based Ripple Carry Adder for IEEE 754 Standards

“…A ripple carry adder [18,19] is a logic circuit which is constructed in a cascaded structure using a series of full adder blocks as shown in Fig. 7.…”

Quasi Delay Insensitive Majority Voters for Triple Modular Redundancy Applications

“…A completion detector is used along with the logic to enforce the strong indication property. To explain this method, the SOP expressions of (1) and (2) are transformed into DSOP expressions, as given by (43) and (44). Equations (43) and (44) are used to synthesize the three-input majority voter which is shown in Figure 9 that corresponds to RTZ handshaking.…”

“…To explain this method, the SOP expressions of (1) and (2) are transformed into DSOP expressions, as given by (43) and (44). Equations (43) and (44) are used to synthesize the three-input majority voter which is shown in Figure 9 that corresponds to RTZ handshaking. In Figure 9, the internal dual rail output (IV1,IV0) is logically equivalent to the dual rail voter output (V1,V0).…”

Indicating Asynchronous Multipliers

“…Among the strong-and weak-indication circuits, the latter are preferable for practical implementation [19], and this is because of the strict timing restrictions inherent in the former. In general, for implementing arithmetic functions, the weakindication type is preferable to the strong-indication type [20][21][22] and this is due to the following reasons: i) strong-indication arithmetic circuits tend to experience worst-case forward and reverse latencies for the application of data and spacer, and therefore the cycle time of strong-indication arithmetic circuits is always the maximum, ii) weak-indication arithmetic circuits may encounter data-dependent forward and reverse latencies or just a data-dependent forward latency and a constant reverse latency, and thus the cycle time of weak-indication arithmetic circuits is generally reduced compared to the strong-indication arithmetic circuits. However, for the weakly indicating asynchronous implementations of the array multiplier considered here, it is noted that their forward and reverse latencies would not be data-dependent or a constant; rather they correspond to the worst-case timing and so the cycle time also corresponds to the worst-case.…”

“…3, corresponding to RTZ or RTO handshaking. However, the constructions of early output quasi-delayinsensitive asynchronous array multipliers using early output full adders of say, [22] and [42] may not be straightforward. This is due to the likelihood of the problem of gate orphans.…”