2016 11th International Design &Amp; Test Symposium (IDT) 2016
DOI: 10.1109/idt.2016.7843030
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Area efficient implementation of ripple carry adder using memristor crossbar arrays

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Cited by 26 publications
(9 citation statements)
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“…Assuming that the term ∆τ is almost negligible compared to T 2 , the overall expression in (12) is simplified in (13). (14).…”
Section: B Performance Analysismentioning
confidence: 99%
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“…Assuming that the term ∆τ is almost negligible compared to T 2 , the overall expression in (12) is simplified in (13). (14).…”
Section: B Performance Analysismentioning
confidence: 99%
“…In this context, several recent contributions have been proposed to enable computation within memristive memory arrays and can be classified in two categories. The first category involves using the memristor as single-level cell (SLC) [10][11][12][13][14][15][16]. The second category includes work that uses the memristor as multi-level cell (MLC) or analog cell [17][18][19].…”
Section: Introductionmentioning
confidence: 99%
“…The MAGIC gates are realized by the RRAM devices connected in series and/or in parallel [5]. The design practices of logic circuits with the MAGIC gates were reported [14][15], and the synthesis methods were studied [16][17]. Nevertheless, the circuit performance decreases for some logic functions, because only the NOR and NOT MAGIC gates can be implemented in the RRAM array.…”
Section: Introductionmentioning
confidence: 99%
“…Subsequently, many improved circuits based on the MAGIC circuit were proposed. By evaluating circuit performance in different ways, it is found that this kind of memristor based circuits with the advantages of reducing circuit area and increasing computing speed [10][11][12][13][14][15]. At the same time, a lot of research has been focused on the MRL circuits composed of memristors and CMOS transistors based on the compatibility of memristor and CMOS transistors.…”
Section: Introductionmentioning
confidence: 99%