Area Efficient Hardware Implementation of Elliptic Curve Cryptography by Iteratively Applying Karatsuba's Method

Abstract

Securing communication channels is especially needed in wireless environments. But applying cipher mechanisms in software is limited by the calculation and energy resources of the mobile devices. If hardware is applied to realize cryptographic operations cost becomes an issue. In this paper we describe an approach which tackles all these three points. We implemented a hardware accelerator for polynomial multiplication in extended Galois fields (GF) applying Karatsuba's method iteratively. With this approach the area consumption is reduced to 2.1 mm 2 in comparison to. 6.2 mm 2 for the standard application of Karatsuba's method i.e. for recursive application. Our approach also reduces the energy consumption to 60 per cent of the original approach. The price we have to pay for these achievement is the increased execution time. In our implementation a polynomial multiplication takes 3 clock cycles whereas the recurisve Karatsuba approach needs only one clock cycle. But considering area, energy and calculation speed we are convinced that the benefits of our approach outweigh its drawback.

VLSI design of Karatsuba integer multipliers and its evaluation

“…The IKM design is based on the approach to Karatsuba algorithm implementations over Galois fields described in Ref. 4. However, calculations over Galois fields do not involve carry operations, so that addition becomes logical XOR, and multiplication becomes logical AND.…”

“…There are also many examples of hardware-based Karatsuba algorithm implementations over a Galois field (GF), for use in elliptic curve cryptography and other fields [4,10]. On the other hand, there are few examples of the implementation and evaluation of hardware Karatsuba multipliers for multidigit operations (e.g., 32-bit Karatsuba integer multiplier [11]), and no studies dealing with the range from hundreds to thousands of bits are available.…”

“…In addition, compact low-power-consumption ASICs are often used instead of general-purpose processors to implement inexpensive embedded devices. Further, multidigit calculations far beyond the bit length of general-purpose processors are required in many fields such as numerical analysis [1], chaos computing [2], primality testing [3], or cryptography [4]. In particular, rounding errors are known to strongly affect the whole calculation in chaos-based image processing [5] and communication systems [6].…”

Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors

“…In case of using the classic school multiplication 65000 XOR and AND operations are needed for multiplication of two 256-bit numbers. By using the iterative Karatsubamultiplication, the number of AND operations can be reduced to 6561 [37]. However, the number of XOR operations remains unchanged.…”

Combining Multiplication Methods with Optimized Processing Sequence for Polynomial Multiplier in GF(2 k )

“…An additional means to improve the chip-parameters of the multipliers is the reducing the number of additions (XOR-operations). This reduction can be achieved by using pre-defined processing sequences for additions of partial products [11]. If an optimal combination of several multiplication approaches with a reduced number of XOR-operations is found, the area and energy consumption is reduced significantly.…”