Area efficient controller design of barrel shifters for reconfigurable LDPC decoders

Oh, Daesun; Parhi, Keshab K.

doi:10.1109/iscas.2008.4541399

Cited by 11 publications

(9 citation statements)

References 9 publications

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“…This way, all of these control bits of a Benes network can be obtained. The proposed algorithm outperforms the one presented in [10] in the following two aspects.…”

Section: Algorithmmentioning

confidence: 86%

“…The critical path of the SG module is shorter. The critical path of the controller in [10] is T DECODER + (K/2) · T OR + T AND + T XOR , where K is the size of a sub-Benes network. K can be very large in general.…”

Section: In Any Conditionmentioning

confidence: 99%

“…Although this approach can reduce the hardware complexity compared with the direct implementation using M M-to-1 multiplexers when the size of submatrix is M , it still suffers from significant hardware overhead. A novel controller design of barrel shifters for reconfigurable LDPC decoders using the Benes network structure was most recently presented in [10], in which control signals for switches are computed on the fly. However, those signals for switches within one stage are generated in serial, which increases the overall latency of the shuffle network.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders

Lin

Wang

et al. 2009

IEEE Trans. Circuits Syst. II

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In this brief, a new algorithm that can efficiently generate all the control signals for the shuffle network used in flexible low-density parity-check (LDPC) decoders is proposed. Employing the proposed algorithm, the hardware complexity of the controller of shuffle networks using the Benes network structure can be significantly reduced. In addition, a low-complexity reconfigurable shuffle network architecture for flexible LDPC decoders is developed. Both the Benes network and the controller can be tailored to fit specific applications. Consequently, an efficient shuffle network for WiMAX LDPC decoders is presented. Synthesis results demonstrate that with the SMIC 0.18-μm complementary metal-oxide-semiconductor process, the total gate count of the proposed shuffle network is only 16 000. The area saving is between 26.6% and 71.1% compared to related works in the literature.

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“…This way, all of these control bits of a Benes network can be obtained. The proposed algorithm outperforms the one presented in [10] in the following two aspects.…”

Section: Algorithmmentioning

confidence: 86%

Section: In Any Conditionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders

Lin

Wang

et al. 2009

IEEE Trans. Circuits Syst. II

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“…The existing schemes to implement switch networks include the MS-CS network [20] and Benes network [13,21,22]. The former structure can handle the case when S is not a power of 2, while the latter is proved more efficient in area and gate count.…”

Section: The Reconfigurable Switch Networkmentioning

confidence: 99%

Systematic construction, verification and implementation methodology for LDPC codes

Cui

Wang

et al. 2012

J Wireless Com Network

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In this article, a novel and systematic Low-density parity-check (LDPC) code construction, verification and implementation methodology is proposed. The methodology is composed by the simulated annealing based LDPC code constructor, the GPU based high-speed code selector, the ant colony optimization based pipeline scheduler and the FPGA-based hardware implementer. Compared to the traditional ways, this methodology enables us to construct both decoding-performance-aware and hardware-efficiency-aware LDPC codes in a short time. Simulation results show that the generated codes have much less cycles (length 6 cycles eliminated) and memory conflicts (75% reduction on idle clocks), while having no BER performance loss compared to WiMAX codes. Additionally, the simulation speeds up by 490 times under float precision against CPU and a net throughput 24.5 Mbps is achieved. Finally, a net throughput 1.2 Gbps (bit-throughput 2.4 Gbps) multi-mode LDPC decoder is implemented on FPGA, with completely on-the-fly configurations and less than 0.2 dB BER performance loss.

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“…Liu et al [14] designed a self-routing network for the IEEE 802.11n and 806.16e standards with a barrel shifter and two extra stages of multiplexors. The most recent approach in this category is by Oh and Parhi [11], [13], which we call Oh-Parhi network (OPN) in the rest of this paper. The key insight in the OPN is given as follows: Given that P M is not always a power of two, instead of using only 2 × 2 switches, the OPN proposes the use of other types of primitive switches, such as 3 × 3 or 5 × 5, to reduce the area and control complexity.…”

Section: Introductionmentioning

confidence: 99%

QSN—A Simple Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders

Chen

Lin

Akella

2010

IEEE Trans. Circuits Syst. II

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There is an increasing need for configurable quasicyclic low-density parity-check (QC-LDPC) decoders that can support a family of structurally compatible codes instead of a single code. The key component in a configurable QC-LDPC decoder is a programmable circular-shift network that supports cyclic shifts of any size up to a predefined maximum submatrix size. This paper presents a QC-LDPC shift network (QSN), which has two key advantages over state-of-the-art solutions in recent literature. First, the QSN reduces the number of stages in the critical path, which improves the clock frequency and makes it scalable, particularly in a field-programmable gate array (FPGA)-based implementation where an interconnect delay is dominant. Second, the QSN's control logic is simple to generate and occupies a significantly smaller area. The QSNs for a variety of codes suitable for emerging applications are implemented, targeting both a 180-nm Taiwan Semiconductor Manufacturing Company Ltd. complimentary metal-oxide-semiconductor library and a Xilinx Virtex 4 FPGA. The proposed implementation is shown to be 2.1 times faster than the best known implementation in literature and requires almost eight times less control area. Furthermore, this paper presents analytical models of the critical-path and datapath complexity for arbitrary-sized submatrices and proves that the QSN indeed generates all the output combinations required for implementing reconfigurable QC-LDPC decoders.

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Area efficient controller design of barrel shifters for reconfigurable LDPC decoders

Cited by 11 publications

References 9 publications

Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders

Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders

Systematic construction, verification and implementation methodology for LDPC codes

QSN—A Simple Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders

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