2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 2014
DOI: 10.1109/apccas.2014.7032811
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Area-efficient check node unit architecture for single block-row quasi-cyclic LDPC codes

Chuan Zhang
1
,
Shenghui Weng
2
,
Xiaohu You
3
et al.
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Cited by 3 publications
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An Enhanced Check-Node Architecture for 5G New Radio LDPC Decoders

Ghaffari
1
,
Le
2
2021
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)
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An Enhanced Check-Node Architecture for 5G New Radio LDPC Decoders

Ghaffari
1
,
Le
2
2021
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)
0
0
0
0
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Design of High-Performance and Area-Efficient Decoder for 5G LDPC Codes

Cui
1
,
Ghaffari
2
,
Le
3
et al. 2021
IEEE Trans. Circuits Syst. I
29
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3
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Area-Efficient QC-LDPC Decoding Architecture With Thermometer Code-Based Sorting and Relative Quasi-Cyclic Shifting

Jang,
Jang,
Kim
et al. 2024
IEEE Trans. Circuits Syst. I
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