2011
DOI: 10.1016/j.sysarc.2010.10.009
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Area and power-efficient innovative congestion-aware Network-on-Chip architecture

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Cited by 34 publications
(29 citation statements)
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“…Figure 2 (b) shows the view of heterogeneous mesh with diagonal links. This design, taking full advantage of abundant wiring tracks, is widely adopted in literatures, such as work [4,5,6]. In case of fig 2 (b), we can observe that there is higher bandwidth and buffer density in the center of heterogeneous mesh network than the peripheral area of network, which can better map the aggregated traffic of mesh network and shorten the network diameter.…”
Section: A Design Of Basically Heterogeneous Mesh Unitmentioning
confidence: 99%
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“…Figure 2 (b) shows the view of heterogeneous mesh with diagonal links. This design, taking full advantage of abundant wiring tracks, is widely adopted in literatures, such as work [4,5,6]. In case of fig 2 (b), we can observe that there is higher bandwidth and buffer density in the center of heterogeneous mesh network than the peripheral area of network, which can better map the aggregated traffic of mesh network and shorten the network diameter.…”
Section: A Design Of Basically Heterogeneous Mesh Unitmentioning
confidence: 99%
“…In these topologies, the mesh network is the most widely studied in research and employed in prototype systems due to its better scalability, regularity and ease of implementation in silicon. Recently, many variants of mesh had been proposed [5,6]. In these mesh variant, scarce resources like buffers and bandwidth are uniformly distributed in all nodes.…”
Section: Introductionmentioning
confidence: 99%
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