Architectures for silicon nanoelectronics and beyond

We propose two fault tolerance techniques for hybrid CMOS/nano architecture implementing logic functions as Look-Up Tables. We compare the efficiency of the proposed techniques with recently reported methods that use single coding schemes in tolerating high fault rates in nanoscale fabrics. Both proposed techniques are based on error correcting codes to tackle different fault rates. In the first technique, we implement a combined two dimensional coding scheme using Hamming and BCH codes to address fault rates greater than 5%. In the second technique, Hamming coding is complemented with Bad Line Exclusion technique to tolerate fault rates higher than the first proposed technique (up to 20%). We have also estimated the improvement that can be achieved in the circuit reliability in the presence of Don't Care Conditions. The area, latency and energy costs of the proposed techniques were also estimated in the CMOS domain.

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“…Conditions using BCH (15,7,2), which adds 8 parity bits in order to detect and correct 2 errors in the codeword.…”

Section: B Bose-chaudhuri-hocquenghem (Bch)mentioning

confidence: 99%

“…The realisation of fault tolerance in nano/CMOS nanoelectronic architecture will incur area, energy and operational latency overhead in CMOS domain [15]. Such overhead must be taken into account when investigating and evaluating hybrid CMOS/nanodevice fault tolerant architectures.…”

Section: B Hamming With Bad Line Exclusion : Techniquementioning

confidence: 99%

Fault-tolerance techniques for hybrid CMOS/nanoarchitecture

Melouki

Srivastava

Al-Hashimi

2010

IET Computers &Amp; Digital Techniques

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“…In order to discover free rooms for further performance and functionality improvements, a number of emerging nano-devices, e.g., Doped/Schottky Barrier Silicon NanoWire FETs (SiNWFETs), various types of Fin-Shaped FETs, and Carbon Nanotube FETs (CNTFETs) have been proposed by research community [2]- [5]. Due to their novel and complex geometries, they introduce new challenges such as additional sources of variation which makes the statistical variation analysis challenging [7].…”

Section: Introductionmentioning

confidence: 99%

A fast TCAD-based methodology for Variation analysis of emerging nano-devices

Mohammadi

Gaillardon

Yazdani

et al. 2013

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

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Abstract-Variability analysis of nanoscale transistors and circuits is emerging as a necessity at advanced technology nodes. Technology Computer Aided Design (TCAD) tools are powerful ways to get an accurate insight of Process Variations (PV). However, obtaining both fast and accurate device simulations is impractical with current TCAD solvers. In this paper, we propose an automated output prediction method suited for fast PV analysis. Coupled with TCAD simulations, our methodology can substantially reduce the time complexity and cost of variation analysis for emerging technologies. We overcome the simulation obstacles and preserve accuracy, using a neural network based regression to predict the output of individual process simulations. Experiments indicate that, after the training process, the proposed methodology effectively accelerate TCAD-based PV simulations close to compact-model-based simulations. Therefore, the methodology can be an excellent opportunity in enabling extensive statistical simulations such as Monte-Carlo for emerging nano-devices.

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“…These circuits will not only more susceptible to errors, but will also have high defect rates. Systems employing nano components will presumably have to deal with non-negligible error rates [1], [2], and [7]. The error effects can be corrected using techniques such as hardware/time redundancy [16], error-correcting information encoding [8] and [19], software-based fault tolerance [20], or combinations thereof [15] and [18].…”

Section: Introductionmentioning

confidence: 99%

LUT-based FPGA technology mapping for reliability

Cong

Minkovich

2010

Proceedings of the 47th Design Automation Conference

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As device size shrinks to the nanometer range, FPGAs are increasingly prone to manufacturing defects. We anticipate that the ability to tolerate multiple defects will be very important at 45nm and beyond. One common defect point is in the lookup table (LUT) configuration bits, which are crucial to the correct operation of FPGAs. In this work we will present an error analysis technique that is able to efficiently calculate the number of critical bits needed to implement each LUT. We will perform this analysis using a scalable overlapping window-based method called DCOW (Don't-care Computation with Overlapping Windows), which allows for accurate and efficient don't-care lower bound calculations. This new windowing technique can approximate the complete don't cares within 2.34%, and can be used for many logic synthesis operations. In particular, we apply DCOW to our FPGA mapping algorithm to reduce the number of possible faults. This will allow the design to have a much higher success of functioning correctly when implemented on a faulty FPGA. By using our algorithm, we are able to reduce the number of possible faults by more than 12% with no area increase.

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Architectures for silicon nanoelectronics and beyond

Cited by 77 publications

References 2 publications

Fault-tolerance techniques for hybrid CMOS/nanoarchitecture

Fault-tolerance techniques for hybrid CMOS/nanoarchitecture

A fast TCAD-based methodology for Variation analysis of emerging nano-devices

LUT-based FPGA technology mapping for reliability

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