1989
DOI: 10.1117/12.7977048
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Architectures For Focal Plane Image Processing

Abstract: Abstract. Architectures for focal plane image processing are discussed. On-chip image preprocessing for solid-state imagers using analog CCD circuits is described for low, medium, and high density detector arrays. A spatially parallel architecture for low density, high throughput applica tions is described. For sparse illumination or event detection, a content· addressable architecture is proposed. A new pipelined vector pixel pro· cessor architecture for medium density infrared staring focal plane ar rays is … Show more

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Cited by 39 publications
(14 citation statements)
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“…If is the remainder of , . According to the definition of , can be expressed by (1) If is large, the ratio can be approximated as (2) If is greater than , then the period for which the MLE output is logic one is clock cycles. Thus, MLE outputs of logic one occur within clock cycles, where is the quotient of .…”
Section: A Analysis Of Angular Velocity Selectivity For a Single-edgmentioning
confidence: 99%
“…If is the remainder of , . According to the definition of , can be expressed by (1) If is large, the ratio can be approximated as (2) If is greater than , then the period for which the MLE output is logic one is clock cycles. Thus, MLE outputs of logic one occur within clock cycles, where is the quotient of .…”
Section: A Analysis Of Angular Velocity Selectivity For a Single-edgmentioning
confidence: 99%
“…(1) pixel-by-pixel multiplication of a region of interest of image I(r, y) by the kernel K(x, y), (2) addition of all the products of (1), and (3) shifting K(x. y) by one pixel to the next new position and repeat (1) and (2) until the entire image is processed. Due to the amount of computation and the large size of image data, an convolution unit suitable for analog VLSI implementation is yet to be designed and built.…”
Section: Introductionmentioning
confidence: 99%
“…Other CMOS-based active pixels for current-mode readout [3] and logarithmic companding [4] have also been reported. It has been suggested that on-chip frame memory would enhance the ability to perform certain image processing tasks on chip [5] including frame-to-frame difference encoding, motion detection, and variable resolution imaging.…”
Section: Introductionmentioning
confidence: 99%