Architectures and algorithms for synthesizable embedded programmable logic cores

Abstract

As integrated circuits become more and more complex, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programmable logic cores. Currently, such cores are available from vendors in the form of a "hard" layout. In this paper, we focus on an alternative approach: vendors supply a synthesizable version of their programmable logic core (a "soft" core) and the integrated circuit designer synthesizes the programmable logic fabric using standard cells. Although this technique suffers increased speed, density, and power overhead, the task of integrating such cores is far easier than the task of integrating "hard" cores into an ASIC. For very small amounts of logic, this ease of use may be more important than the increased overhead. This paper presents two synthesizable programmable logic core architectures, describes the associated place and route CAD tools, and compares the two architectures to each other, and to a "hard" programmable logic core. It also shows how these cores can be made more efficient by creating a non-rectangular architecture, an option not available to "hard" core vendors.

SoC implementation issues for synthesizable embedded programmable logic cores

“…Without knowing the logic function that will eventually be implemented in the core, it is difficult to estimate the amount of programmable logic required. We designed two potential logic functions that might be implemented in the core, and measured the size of the core that would be required to implement each function (using custom-built CAD tools described in [9]). For our circuit, we found that a core consisting of forty-nine 3-LUTs would be sufficient for both potential logic functions; however, to allow some safety margin and anticipation of larger functions, a core consisting of sixty-four 3-input LUTs was used.…”

“…Unlike an embedded memory (which could also be used to provide a programmable implementation of the next state logic), the programmable logic core described in [9] is generous in the number of inputs. Furthermore, the size of the core increases only linearly as the number of inputs increases (as opposed to the exponential increase in the size of an embedded memory).…”

“…Our synthesizable programmable logic core required 560x more chip area than the fixed logic that it replaced. Using estimates from [9], the synthesizable core requires 6.4x more area that a hard programmable logic core. These numbers are summarized in Table 1.…”

“…In [9], an alternative technique is described which speaks to the second of these concerns. In this technique, core vendors supply a synthesizable version of their programmable logic core (a "soft" core) and the integrated circuit designer synthesizes the programmable logic fabric using standard cells.…”

“…In this paper, we describe an integrated circuit implemented using the "synthesizable embedded core" technique from [9]. A small network interface circuit was divided into a programmable portion and a fixed portion.…”