Architecture optimization of SPAD integrated in 28 nm FD-SOI CMOS technology to reduce the DCR

Issartel, Dylan; Cellier, Rémy; Calmon, Françis; Gao, S. H.; Golanski, Dominique; Pittet, Patrick; Cathelin, Andreia

doi:10.1016/j.sse.2022.108297

Cited by 7 publications

(6 citation statements)

References 21 publications

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“…Firstly, the threshold voltage 𝑉 increase with temperature (+11 mV/°C) is a signature of the impact ionization avalanche mechanism in the SPAD multiplication zone. The increase in the DCR with excess voltage is more abrupt in the presence of STI patterning due to afterpulsing runaway, as observed in previous studies [15,16]. This phenomenon will have the effect of limiting the maximum excess voltage to around 0.65 V (4% of breakdown voltage 𝑉 ) for 𝐹𝐹 = 15% and to around 0.8 V (5% of 𝑉 ) for 𝐹𝐹 = 25%.…”

Section: Dark Count Rate (Dcr) Experimental Resultssupporting

confidence: 63%

“…This higher relative gain increase with excess voltage for the patterned SPAD compared to the reference structure can be partially explained by the higher increase in (i) the avalanche triggering probability 𝑃 , and in (ii) the number of photogenerated carriers. Indeed, according to a previous TCAD study [15], a…”

Section: Discussionmentioning

confidence: 99%

“…Figure 6b illustrates the layout of a quasi-circular SPAD with an inset showing the STI patterning above the photosensitive area. The standard process was used (except for the modified Deep N-well implantation [15]) including all BEOL layers but no antireflective coating (ARC) or micro-lenses were implemented. We can assume that very little light reaches the CMOS electronics because all the Back-End-Of-Line (BEOL) layers (including the metallic dummy structures) are present and screen the light.…”

Section: Test Chip Presentationmentioning

confidence: 99%

“…SPAD FD-SOI devices are implemented below the buried oxide (BOX) layer and the electronic logic circuits are inserted into the thin silicon layer on top of the BOX layer, which provides an intrinsic 3D stack and a much higher fill factor considering BSI. Different architecture variants were studied to assess the impact of the Shallow Trench Isolation (STI) location and density on the performance of the SPAD FD-SOI, particularly in terms of the Dark Count Rate (DCR) and PDP [15]. Experimental measurements correlated with simulation results on SPADs FD-SOI with non-passivated STI trenches have shown that the overall DCR increases with STI density at high excess voltage [16].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Shallow Trench Isolation Patterning to Improve Photon Detection Probability of Single-Photon Avalanche Diodes Integrated in FD-SOI CMOS Technology

Gao,

Vu,

Cazimajou

et al. 2024

Photonics

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The integration of Single-Photon Avalanche Diodes (SPADs) in CMOS Fully Depleted Silicon-On-Insulator (FD-SOI) technology under a buried oxide (BOX) layer and a silicon film containing transistors makes it possible to realize a 3D SPAD at the chip level. In our study, a nanostructurated layer created by an optimized arrangement of Shallow Trench Isolation (STI) above the photosensitive zone generates constructive interferences and consequently an increase in the light sensitivity in the frontside illumination. A simulation methodology is presented that couples electrical and optical data in order to optimize the STI trenches (size and period) and to estimate the Photon Detection Probability (PDP) gain. Then, a test chip was designed, manufactured, and characterized, demonstrating the PDP improvement due to the STI nanostructuring while maintaining a comparable Dark Count Rate (DCR).

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Section: Dark Count Rate (Dcr) Experimental Resultssupporting

confidence: 63%

Section: Discussionmentioning

confidence: 99%

Section: Test Chip Presentationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Shallow Trench Isolation Patterning to Improve Photon Detection Probability of Single-Photon Avalanche Diodes Integrated in FD-SOI CMOS Technology

Gao,

Vu,

Cazimajou

et al. 2024

Photonics

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“…The designed sorter algorithmic program was simulated using Xilinx ISE 14.7 on Virtex-7, it is optimized and integrated for 28nm for the best performance (21) , and the complete specification of the board on which it was synthesized is xc7vx415tffg1158-1. The results of the proposed sorter are compared with other sorter methods such as Bitonic, Insertion, Selection, and Bubble with various parameters.…”

Section: Resultsmentioning

confidence: 99%

FPGA Design for Low Delay Comparison-free, Odd-even Merge Sorter

Preethi¹,

Mohan²,

Augustine³

et al. 2022

IJST

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Background/Objective: Reduced Instruction Set Computer (RISC) is one of the most common types of architecture involved in microprocessor that has several blocks. There is a lot of scope that can be observed in optimizing these blocks involved in RISC resulting in better and effective microprocessors. Method: One of the sub-blocks that plays a prominent role in RISC architecture is sorter, and it can be achieved by modifying the sorting algorithm. Findings: A novel odd-even comparison-free sorting that assists in arranging N several data components in roughly N clock cycles is proposed here. N identical blocks are arranged in streamlined manner that are stacked using handful primary logic elements resulting in sorter computation. In the proposed framework, classification and categorization activities are executed in a channeled fashion. The entire design is amalgamated for numerous data sets from imitated indiscriminately generated data elements to all exceptional elements, to all the similar elements, and also from random to completely sorted data elements. It has been observed that, the algorithm appears impartial to the input ordering. Novelty: comparison-free unit was implemented on odd-even sorter. Synthesis results indicate that the proposed approach consumes reasonably low FPGA resource. The number of elements consider for sorting was N=8, this architecture takes per element sorting delay as approximately 2.1 to 4.4 ns (1 clock cycle).

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Integration of an ultra-fast active quenching circuit with a monolithic 3D SPAD pixel in a 28 nm FD-SOI CMOS technology

Lakeh,

Kammerer,

Schell

et al. 2023

Sensors and Actuators A: Physical

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Architecture optimization of SPAD integrated in 28 nm FD-SOI CMOS technology to reduce the DCR

Cited by 7 publications

References 21 publications

Shallow Trench Isolation Patterning to Improve Photon Detection Probability of Single-Photon Avalanche Diodes Integrated in FD-SOI CMOS Technology

Shallow Trench Isolation Patterning to Improve Photon Detection Probability of Single-Photon Avalanche Diodes Integrated in FD-SOI CMOS Technology

FPGA Design for Low Delay Comparison-free, Odd-even Merge Sorter

Integration of an ultra-fast active quenching circuit with a monolithic 3D SPAD pixel in a 28 nm FD-SOI CMOS technology

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