Architecture of fault-tolerant computers: an historical perspective

Siemwiorek, D.P.

doi:10.1109/5.119549

Cited by 46 publications

(13 citation statements)

References 57 publications

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“…Redundancy is one of the most fundamental approaches to achieving reliability (Siemwiorek 1991), and also to achieving resilience (Alsberg and Day 1976). In most cases, redundancy refers to deploying into a system more components than are required for the functionality.…”

Section: Redundancymentioning

confidence: 99%

Architectural design for resilience

Liu

Deters

Zhang

2010

Enterprise Information Systems

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Section: Redundancymentioning

confidence: 99%

Architectural design for resilience

Liu

Deters

Zhang

2010

Enterprise Information Systems

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“…In this case, a circuit module is triplicated and the corresponding output vectors are merged through a majority voter [11] [12]. Several investigations aimed at enhancing this basic idea.…”

Section: Introductionmentioning

confidence: 99%

Functional enhancements of TMR for power efficient and error resilient ASIC designs

Sämrow

Cornelius

Gorski

et al. 2011

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

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Progressive technology scaling raises the need for efficient VLSI design methods facing the increasing vulnerability to permanent physical defects, while considering power efficiency of resulting circuit implementations at the same time. Triple Modular Redundancy (TMR) represents a common method to encounter reliability problems, but has the drawback of increased area and power consumption. This work introduces a Low Power Redundant (LPR) design solution that targets the power penalty of TMR implementations. This is done by enhanced and new functional runtime capabilities for error detection and operation control. By exploiting the inherent modularity and parallelism of TMR, the LPR solution applies additional control logic to switch dynamically between compare phases (to indicate faults and their locations) and parallel operation (with reduced operation frequency). This allows power optimized circuit operation with full support for the treatment of permanent faults. Simulation results on different ALU implementations show a decrease of power consumption of up to 60 % compared to conventional TMR. Furthermore, different strategies for the switching between operation modes are introduced that enable power efficient system operation in the presence of permanent physical defects. Moreover, significant reliability improvements are also achieved due to the adaptive use of the redundant modules.

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“…NASA has supported this type of fault tolerance throughout its history. The Saturn V launch vehicle used triple modular redundancy to control flight path adjustments, and the Space Shuttle uses software voting on the outputs of four modules (computers) for general control (Siewiorek 1991).…”

Section: Introductionmentioning

confidence: 99%

An optimal single error locating TSC-TMRsystem

Jumaily¹,

Bataineh²

1997

International Journal of Electronics

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A triple modular redundancy (TMR) system incorporates majority voting to achieve fault tolerance, although not all single faults can be tolerated due to the possibility of voter failure. A totally self-checking (TSC) circuit is introduced to monitor the TMR system; it receives the outputs of each module and that of the voter to generate three system statuses, and three module status outputs. The TSC± TMR system has the capability to detect all single fault occurrences inclusive of the checking circuitry, thus achieving optimum availability and maintainability regarding single fault occurrences. Morphic Boolean algebra forms the basis of the TSC fault detecting circuit design. Morphic building blocks constitute the newly designed checking circuit.

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Architecture of fault-tolerant computers: an historical perspective

Cited by 46 publications

References 57 publications

Architectural design for resilience

Architectural design for resilience

Functional enhancements of TMR for power efficient and error resilient ASIC designs

An optimal single error locating TSC-TMRsystem

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