Architecture implications of pads as a scarce resource

Zhang, Runjie; Wang, Ke; Meyer, Brett H.; Stan, Mircea R.; Skadron, Kevin

doi:10.1109/isca.2014.6853199

Cited by 42 publications

(16 citation statements)

References 23 publications

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“…Combined with a detailed EM lifetime study, we show that with a performance overhead of just 1%, chip I/O bandwidth can be tripled without sacrificing EM lifetime. More sensitivity and limit studies are available in a technical report [40].…”

Section: Discussionmentioning

confidence: 99%

Architecture implications of pads as a scarce resource

Zhang

Wang

Meyer

et al. 2014

SIGARCH Comput. Archit. News

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Section: Discussionmentioning

confidence: 99%

Architecture implications of pads as a scarce resource

Zhang

Wang

Meyer

et al. 2014

SIGARCH Comput. Archit. News

Self Cite

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“…Researchers [11] from IBM also observe the C4 pad shortage and propose to utilize the heat sink to deliver power. A recent work demonstrates the impact of the pad shortage on power delivery quality [37]. In another recent work, Chen et.…”

Section: Related Work and Backgroundmentioning

confidence: 96%

Powering Up Dark Silicon: Mitigating the Limitation of Power Delivery via Dynamic Pin Switching

Chen

Peng

et al. 2015

IEEE Trans. Emerg. Topics Comput.

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The end of Dennard Scaling has led to a large amount of inactive or significantly under-clocked transistors on modern chip multiprocessors in order to comply with the power budget and prevent the processors from overheating. This so-called "dark silicon" is one of the most critical constraints that will hinder the scaling with Moore's Law in the future. While advanced cooling techniques, such as liquid cooling, can effectively decrease the chip temperature and alleviate the power constraints; the peak performance, determined by the maximum number of transistors which are allowed to switch simultaneously, is still confined by the amount of power pins on the chip package. In this paper, we propose a novel mechanism to power up the dark silicon by dynamically switching a portion of I/O pins to power pins when offchip communications are less frequent. By enabling extra cores or increasing processor frequency, the proposed strategy can significantly boost performance compared with traditional designs.Index Terms-Multiprocessor Systems, Impact of VLSI on system design, Design studies.

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“…Voltspot [24] to identify the interval including the worst PSN. Then, we back-annotate the interval to the original power trace segment for the PDN stimuli extraction.…”

Section: Introduction To Task Graphmentioning

confidence: 99%

Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint

Zhao

Yang

Zhao

et al. 2018

J. Comput. Sci. Technol.

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Thanks to the emerging 3D integration technology, The multiprocessor system-on-chips (MPSoCs) can now integrate more IP cores on chip with improved energy efficiency. However, several severe challenges also rise up for 3D ICs due to the die-stacking architecture. Among them, power supply noise becomes a big concern. In the paper, we investigate power supply noise (PSN) interactions among different cores and tiers and show that PSN variations largely depend on task assignments. On the other hand, high integration density incurs severe thermal issue on 3D ICs. In the paper, we propose a novel Yinglin Zhao and Yuanqing Cheng have equal contributions in this work.

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Architecture implications of pads as a scarce resource

Cited by 42 publications

References 23 publications

Architecture implications of pads as a scarce resource

Architecture implications of pads as a scarce resource

Powering Up Dark Silicon: Mitigating the Limitation of Power Delivery via Dynamic Pin Switching

Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint

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