Architecture implications of pads as a scarce resource

Zhang, Runjie; Wang, Ke; Meyer, Brett H.; Stan, Mircea R.; Skadron, Kevin

doi:10.1145/2678373.2665728

Cited by 17 publications

(22 citation statements)

References 33 publications

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“…In the past, researchers constructed system-level models to examine the supply voltage noise in both 2D ( [6,12]) and 3D ( [5,9]) chips. While prior work has demonstrated that stacking more layers of active silicon using the tradi tional PDN structure will monotonically increase on-chip noise [9], it is still not clear whether, or in which scenarios the V-S scheme provides better power delivery quality (in terms of transient noise) for 3D-ICs.…”

Section: System-level Supply Voltage Noise Modelingmentioning

confidence: 99%

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Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC

Zhang

Mazumdar

Meyer

et al. 2015

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

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Ahstract-Aside from the benefits it brings, 3D-IC technology inevitably exacerbates the difficulty of power delivery with volumetrically increasing power consumption. Recent work managed to "recycle" current within the 3D stack by linking the different layers' supply/ground nets into a series connection. This charge-recycled (also known as voltage-stacked, or V-S) scheme provides a scalable so lution for 3D-IC's power delivery because it supports an arbitrary number of layers with a constant off-chip current demand. Although prior work has studied the circuit im plementation of a V-S power delivery network (PDN) and its current-reduction benefits, a whole-system evaluation of V-S PDNs' transient voltage noise and a noise comparison between the V-S PDN and the traditional PDN are miss ing. In this paper, we build a system-level model to exam ine voltage-stacked 3D-ICs' transient noise and explore the impact of different PDN design parameters and workload behaviors. Our results show that compared with the tra ditional PDN scheme, V-S provides stronger isolation for cross-layer noise interference, which in turn grants higher performance benefits for run-time noise mitigation tech niques, such as dynamic margin adaptation. We observe that, compared with traditional PDNs, V-S PDNs provide up to 60% lower transient noise in the worst-case scenario. Furthermore, we show that V-S PDNs significantly reduce the packaging cost, because their noise is almost insensitive to the package impedance (e.g., a 300% impedance increase only raises worst-case noise by less than 0.3% Vdd).

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Section: System-level Supply Voltage Noise Modelingmentioning

confidence: 99%

“…We then extend an open-source, system-level PDN model, VoltSpot version 1.0 [6], and integrate it with our regulator model, producing the first platform to enable whole-system, tran sient simulation for many-layer 3D-ICs' V-S PDN. This new version of VoltSpot has been released as version 2.0.…”

Section: Introductionmentioning

confidence: 99%

Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC

Zhang

Mazumdar

Meyer

et al. 2015

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

Self Cite

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“…One possible reason is that many past studies have used cores that did not trigger some errors we observed. For example, older and simpler cores like Atom and Penryn have lower issue widths, so studies using them [13,18,42,51,55] avoid read/write port overestimates, one of the major error sources we observed. Penryn cores also do not support SMT, eliminating the duplication of hardware error.…”

Section: Discussion and Guidelinesmentioning

confidence: 97%

“…Significant voltage drops can result in timing violations for logic circuits. To mitigate effects of voltage noise, researchers have proposed various runtime strategies [17,20,26,29,41,55], optimal placement of available C4 pads [51], and more. In this case study, we quantify the amount of error in voltage noise that derives from power error.…”

Section: Voltage Noisementioning

confidence: 99%

“…In this case study, we quantify the amount of error in voltage noise that derives from power error. To evaluate voltage noise characteristics, we constructed an on-chip power distribution network and package model using VoltSpot [55], with parameters derived from the POWER7 chip and package. Because VoltSpot is a very fine grained modeling tool and the C4 pads on POWER7 are very densely packed, we only model a single chiplet -core, L2 and local L3 cache -rather than the full chip like in the thermal study.…”

Section: Voltage Noisementioning

confidence: 99%

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Quantifying sources of error in McPAT and potential impacts on architectural studies

Jacobson

Bose

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

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Architectural power modeling tools are widely used by the computer architecture community for rapid evaluations of high-level design choices and design space explorations. Currently, McPAT [31] is the de facto power model, but the literature does not yet contain a careful examination of its modeling accuracy. In addition, the issue of how greatly power modeling error can affect architectural-level studies has not been quantified before. In this work, we present the first rigorous assessment of McPAT's core power and area models with a detailed, validated power modeling toolchain used in current industrial practice. We find that McPAT's predictions can have significant error because some of the models are either incomplete, too high-level, or assume implementations of structures that differ from that of the core at hand. We demonstrate that large errors are possible when using McPAT's dynamic power estimates in the context of voltage noise and thermal hotspots, but for steady-state properties, accurately modeling leakage power is more important. Based on our analysis, we are able to provide guidelines for creating accurate McPAT models, even without access to detailed industrial power modeling tools. We conclude that in spite of its accuracy gaps, McPAT is still a very useful tool for many architectural studies, and its limitations can often be adequately addressed for a given research study of interest.

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Selective Flip-Flop Optimization for Circuit Reliability

Golanbari

Ebrahimi

Kiamehr

et al. 2020

Dependable Embedded Systems

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This chapter proposes a selective flip-flop optimization method (Golanbari et al., IEEE Trans Very Large Scale Integr VLSI Syst 39(7):1484–1497, 2020; Golanbari et al., Aging guardband reduction through selective flip-flop optimization. In: IEEE European Test Symposium (ETS) (2015)), in which the timing and reliability of the VLSI circuits are improved by optimizing the timing-critical components under severe impact of runtime variations. As flip-flops are vulnerable to aging and supply voltage fluctuation, it is necessary to address these reliability issues in order to improve the overall system lifetime. In the proposed method, we first extend the standard cell libraries by adding optimized versions of the flip-flops designed for better resiliency against severe Bias Temperature Instability (BTI) impact and/or supply voltage fluctuation. Then, we optimize the VLSI circuit by replacing the aging-critical and voltage-drop critical flip-flops of the circuit with optimized versions to improve the timing and reliability of the entire circuit in a cost-effective way. Simulation results show that incorporating the optimized flip-flops in a processor can prolong the circuit lifetime by 36.9%, which translates into better reliability.This chapter is organized as follows. Section 1 introduces wide-voltage operation reliability issues and motivates the proposed selective flip-flop optimization approach. The impacts of runtime variations on flip-flops are explained in Sect. 2. Consequently, Sect. 3 presents cell-level optimization of the flip-flops. The proposed selective flip-flop optimization methodology is described in Sect. 4, and optimization results are discussed in Sect. 5. Finally, Sect. 7 concludes the chapter.

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Architecture implications of pads as a scarce resource

Cited by 17 publications

References 33 publications

Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC

Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC

Quantifying sources of error in McPAT and potential impacts on architectural studies

Selective Flip-Flop Optimization for Circuit Reliability

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