Architecture Design of Versatile Recognition Processor for Sensornet Applications

Hori, Y.; Hanai, Yuya; Nishimura, Takahiro; Kuroda, Tadahiro

doi:10.1109/mm.2009.93

Cited by 2 publications

(3 citation statements)

References 17 publications

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“…[2], [5] measured power consumption from a test chip fabricated by using several power implementation techniques such as multi-threshold voltage. These techniques will help reduce the power consumption when our processor is implemented into a chip.…”

Section: Implementation Resultsmentioning

confidence: 99%

“…Each bank of CM is connected to one OC in each triple classifier, so that the triple classifier can read three feature data in one cycle. In this work, we do not adopt any classifier data compression techniques described in [2], [4] to support OpenCV non-tilted feature types [6]. By applying these techniques, we can reduce the size of CM.…”

Section: Architecture Overviewmentioning

confidence: 99%

“…For that reason, many hardware architectures employing AdaBoost with Haar-like features have been proposed [2]- [5].…”

Section: Introductionmentioning

confidence: 99%

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A low-power Adaboost-based object detection processor using Haar-like features

Kimura

Matai

Jacobsen

et al. 2013

2013 IEEE Third International Conference on Consumer Electronics ¿ Berlin (ICCE-Berlin)

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Abstract-This paper presents an architecture of a low-power real-time object detection processor using Adaboost with HaarLike features. We employ a register array based architecture, and introduce two architectural-level power optimization techniques; signal gating domain for integral image extraction, and low-power integral image update. The power efficiency of our proposed architecture including nine classifiers is estimated to be 0.64mW/fps when handling VGA(640 × 480) 70fps video.

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Section: Implementation Resultsmentioning

confidence: 99%

Section: Architecture Overviewmentioning

confidence: 99%