Architecture and implementation of a bitserial sorter for weighted median filtering

Henning, C.; Noll, Tobias G.

doi:10.1109/cicc.1998.694960

Cited by 6 publications

(2 citation statements)

References 8 publications

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“…This is due to the fact, that the physically optimized median implementation has been optimized for silicon area and energy per sample and not for maximum throughput rate [33]. This is due to the fact, that the physically optimized median implementation has been optimized for silicon area and energy per sample and not for maximum throughput rate [33].…”

Section: Comparison Of Implementations On Different Architecture Blocksmentioning

confidence: 99%

Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip

Blume

Feldkaemper

Noll

2005

J VLSI Sign Process Syst Sign Image Video Technol

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The exploration of the design space for heterogeneous Systems on Chip (SoC) becomes more and more important. As modern SoCs include a variety of different architecture blocks ensuring flexibility as well as highest performance, it is mandatory to prune the design space in an early stage of the design process in order to achieve short innovation cycles for new products. Thus, the goal of this work is to provide estimations of implementation specific parameters like throughput rate, power dissipation and silicon area by means of cost functions featuring reasonable accuracy at low modeling effort. A model based exploration strategy supporting the design flow for heterogeneous SoCs is presented. In order to demonstrate the feasibility of this exploration strategy, in a first step implementation cost parameters are provided for a variety of basic operations frequently required in digital signal processing which were implemented on discrete components like DSPs, FPGAs or dedicated ASICs. These implementation parameters serve as a basis for deriving cost models for the design space exploration concept.

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Section: Comparison Of Implementations On Different Architecture Blocksmentioning

confidence: 99%

Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip

Blume

Feldkaemper

Noll

2005

J VLSI Sign Process Syst Sign Image Video Technol

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“…Many of them are based on sorting algorithm [11,22,23,[25][26][27][28]. They considered the operation of rank-order filtering as two steps: sorting and choosing.…”

Section: Introductionmentioning

confidence: 99%

On VLSI design of rank-order filtering using DCRAM architecture

Lin

Dung

2008

Integration

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This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for realtime speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 μm 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 × 427.7μm 2 and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply.

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