Architecture and compiler co-optimization for high performance computing

Nakamura, Hiroshi; Kondo, Masaaki; Ohneda, T.; Fujita, M.; Chiba, Shigeru; Sato, Mitsuhisa; Boku, Taisuke

doi:10.1109/iwia.2002.1035018

Cited by 5 publications

(2 citation statements)

References 8 publications

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“…For this reason, we investigate a compiler to generate parallelized and optimized code suitable for the SCIMA-SMP. The compiler is based on the OpenMP [4] compiler and the compiler for a single SCIMA processor [10]. However, we perform optimizations and parallelization by hand in this evaluation because the compiler has not reached completion.…”

Section: Performance Evaluation Environmentmentioning

confidence: 99%

Scima-SMP

Takahashi

Kondo

Boku

et al. 2004

Proceedings of the 3rd Workshop on Memory Performance Issues in Conjunction With the 31st International Symposium on Computer A

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In this paper, we propose a processor architecture with programmable on-chip memory for a high-performance SMP (symmetric multi-processor) node named SCIMA-SMP (Software Controlled Integrated Memory Architecture for SMP) with the intent of solving the performance gap problem between a processor and off-chip memory. With special instructions which enable the explicit data transfer between on-chip memory and off-chip memory, this architecture is able to control the data transfer timing and its granularity by the application program, and the SMP bus is utilized efficiently compared with traditional cache-only architecture. Through the performance evaluation based on clock-level simulation for various HPC applications, we confirmed that this architecture largely reduces the bus access cycle by avoiding redundant data transfer and controlling the granularity of the data movement between on-chip and off-chip memory.

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Section: Performance Evaluation Environmentmentioning

confidence: 99%

Scima-SMP

Takahashi

Kondo

Boku

et al. 2004

Proceedings of the 3rd Workshop on Memory Performance Issues in Conjunction With the 31st International Symposium on Computer A

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“…A possibly relevant one is done by Nakamura et al [14], where compiler technologies were employed to reduce memory accesses, consequently improve performance and save memory power.…”

Section: Introductionmentioning

confidence: 99%

A performance and power co-optimization approach for modern processors

Zhu

Wong

Koh

2005

The Fifth International Conference on Computer and Information Technology (CIT'05)

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Array Organization in Parallel Memories

Al-Mouhamed

2004

International Journal of Parallel Programming

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The bandwidth mismatch between processor and main memory is one major limiting problem. Although streamed computations have predictable access patterns their references have little temporal locality and are generally too long to cache. A memory and compiler co-optimization aimed at reducing low-level memory accesses using software and hardware locality optimizations is presented. We propose a scalable and predictable parallel memory based on a compiler synthesis of storage schemes for multi-dimensional arrays that are accessed by an arbitrary but known set of data access patterns. Using algebra of non-singular Boolean matrices, we present analysis of conflict-free access to (1) parallel memories, and (2) alignment networks. Finding a multi-pattern storage scheme is one NP-complete problem. An effective compiler heuristic is proposed for finding a the storage matrix that minimizes overall memory access time. This applies to arbitrary linear patterns and arbitrary alignment networks. It is shown that the proposed storage scheme finds an optimal storage scheme for parallel (1) FFT, and (2) bitonic sorting. The proposed storage scheme outperforms statically optimized storages in the case of power-of-2 multi-stride access. The case of non power-of-2 strides is also addressed. The performance and scalability of the proposed parallel memory and its predictable access time are presented using numerical and multimedia algorithms. It is shown that a memory utilization above 83% is achieved by our storage scheme for 64 memories which largely outperforms previous proposals. Our approach provides a tool for matching the storage pattern with the data access patterns needed for embedded systems running streamed computations with predictable data access patterns.

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Architecture and compiler co-optimization for high performance computing

Cited by 5 publications

References 8 publications

Scima-SMP

Scima-SMP

A performance and power co-optimization approach for modern processors

Array Organization in Parallel Memories

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