Architectural synthesis of an image processing algorithm using IRIS

Trainor, David; Woods, Roger; McCanny, J.V.

doi:10.1109/vlsisp.1995.527488

Cited by 9 publications

(9 citation statements)

References 7 publications

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“…This work described in this chapter, acts to solve the implementation-level issues during architectural synthesis for FPGA-based DSP design. The work is based on the existing architectural tools, IRIS (Trainor et al 1997), which was developed at Queen's University Belfast and originally targeted at VLSI. The corresponding synthesis methodology in the IRIS architectural synthesis tools is reviewed in following sections.…”

Section: Iris Behavioural Synthesis Toolmentioning

confidence: 99%

Final Statements

2008

FPGA‐Based Implementation of Signal Processing Systems

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Designations used by companies to distinguish their products are often claimed as trademarks. All brand names and product names used in this book are trade names, service marks, trademarks or registered trademarks of their respective owners. The publisher is not associated with any product or vendor mentioned in this book. This publication is designed to provide accurate and authoritative information in regard to the subject matter covered. It is sold on the understanding that the publisher is not engaged in rendering professional services. If professional advice or other expert assistance is required, the services of a competent professional should be sought. Library of Congress Cataloging-in-Publication DataWood, Roger.FPGA-based implementation of complex signal processing systems / Roger Wood ... [et al.]. p. cm. Includes bibliographical references and index.

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Section: Iris Behavioural Synthesis Toolmentioning

confidence: 99%

Final Statements

2008

FPGA‐Based Implementation of Signal Processing Systems

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“…The retiming technique used in this circuit is one which has been used previously for FPGA circuit synthesis 8 . Retiming changes the location of delay elements in a circuit without affecting the input/output characteristics of the circuit 6 .It is used here to produce properly timed circuits when the zero latency algorithm graph nodes are replaced with physical processor nodes with finite latencies.…”

Section: Sfg Retiming For Circuit Implementationmentioning

confidence: 99%

Design technologies for DSP algorithm implementation on heterogeneous architectures

et al. 2003

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Computationally intensive digital signal processing (DSP) systems sometimes have real time requirements beyond that which programmable processor platform solutions, consisting of RISC and DSP processors, can achieve. The addition of Field Programmable Gate Array (FPGA) components to these platforms provides a configurable hardware resource where increased parallelism levels allow very large computational rates. Techniques to implement circuit architectures from signal flow graph (SFG) algorithm expression can produce highly efficient processor implementations. Applying folding transformations produces implementations where hardware resource usage is reduced at the possible expense of throughput. In this paper a new development methodology is presented which analyses the SFG algorithm to suggest appropriate folding techniques. By characterizing different folding techniques, a template circuit architecture can be created early in the design process which does not alter throughout the remainder of the implementation process. Retiming techniques applied to the algorithm SFG produces the properly timed implementation from the template. By applying this methodology, architectural exploration can be quickly and efficiently performed to generate a set of implementations (an 'implementation space') to best meet the constraints of the system. When applied to a Normalised Lattice Filter design example, the results demonstrate high savings on FPGA resource usage, with little reduction in real time performance, demonstrating the implementation advantage of employing this methodology.

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“…The RT-level model proposed in [3] provides an interesting approach to the problem of multirate timing and interfacing but requires a master clock that is potentially much faster than any of the data rates in the system in order to synchronize the interfaces. Models such as the processor timing data used in [7] capture the effects of real system parameters and latency for single rate systems, but they do not provide ways to take advantage of skewed clock phases or multirate graphs directly. The discrete-time domain in Ptolemy II [8] introduces the concept of token time-lines, which helps to achieve greater understandability and analyzability of SDF graphs but does not provide the complete hierarchical timing analysis for which we aim.…”

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confidence: 99%

The hierarchical timing pair model for multirate DSP applications

Chandrachoodan

Bhattacharyya

Liu

2004

IEEE Trans. Signal Process.

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Abstract-The problem of representing timing information associated with functions in a dataflow graph is considered. This information is used for constraint analysis during behavioral synthesis of appropriate architectures for implementing the graph. Conventional models for timing suffer from shortcomings that make it difficult to represent timing information in a hierarchical manner for sequential and multirate systems. Some of these shortcomings are identified, and an alternate timing model that does not have these problems for hardware implementations is provided.We introduce the concept of timing pairs to model delay elements in sequential and multirate circuits and show how this allows us to derive hierarchical timing information for complex circuits. The resulting compact representation of the timing information can be used to streamline system performance analysis. In addition, several analytical results that previously applied only to single rate systems can now be extended to multirate systems.We present an algorithm to compute the timing parameters and have used this to compute timing parameters for a number of benchmark circuits. The results obtained on several ISCAS benchmark circuits as well as several multirate dataflow graphs corresponding to useful signal processing applications are presented. These results show that the new representation model can result in large reductions in the amount of information required to represent timing for hierarchical systems.

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Architectural synthesis of an image processing algorithm using IRIS

Cited by 9 publications

References 7 publications

Final Statements

Final Statements

Design technologies for DSP algorithm implementation on heterogeneous architectures

The hierarchical timing pair model for multirate DSP applications

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