Architectural Leakage-Aware Management of Partitioned Scratchpad Memories

Golubeva,; Loghi,; Poncino,; Macii,

doi:10.1109/date.2007.364541

Cited by 15 publications

(11 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Therefore several recent papers address the problem of leakage power in embedded processors. Golubeva et al [7] investigate scratchpad memories, on-chip memories that are managed by the application and are often used to replace caches in embedded processors. To better exploit on-chip caches, Zhang [28] proposes dynamic allocation of the on-chip cache resources for instructions and data as needed at run time.…”

Section: Article In Pressmentioning

confidence: 99%

See 1 more Smart Citation

Reducing leakage power with BTB access prediction

Kahn

Weiss

2010

Integration

View full text Add to dashboard Cite

Section: Article In Pressmentioning

confidence: 99%

“…Power used by branch predictors is significant [9]. The branch prediction mechanism typically dissipates about 7% and as much as 10% of the processor's power, and the BTB typically dissipates about 7 8 of the power dissipated by the branch predictor overall [18].…”

Section: Introductionmentioning

confidence: 99%

Reducing leakage power with BTB access prediction

Kahn

Weiss

2010

Integration

View full text Add to dashboard Cite

“…When more cores are integrated onto embedded processors, The most important issue of SPM optimization for MPSoC is that how to allocate SPM for multi-cores. SPM can be allocated through new approaches according to the recent research [12][13][14]. The existing works show that SPM optimization can help embedded system to save energy and improve performance.…”

Section: Introductionmentioning

confidence: 99%

Scratchpad memory based power efficient optimization for MPSoC

2011

2011 International Conference on Electronics, Communications and Control (ICECC)

View full text Add to dashboard Cite

With the development of semiconductor technology, more modules are integrated onto a single chip. Multiprocessor system-on-chip (MPSoC) is such circuit with multiple embedded processor cores on chip. It provides high parallelism with multithreads through the multiple cores. Memory system is still the bottleneck of the performance and power-consumption of MPSoC systems. Scratchpad memory (SPM), which is softwarecontrolled on-chip memory without extra tags, is used on MPSoC chips. SPM has low power-consumption and high efficiency compared to cache. However, the SPM requirements from different cores will be also different. How to balance the utilization of SPM is still a challenge. In this paper, we propose a new technique for SPM allocation on demand to reduce the power consumption and improve the performance of MPSoC. SPM will be shared under special constrains. Experimental results show that our approach can reduce both the execution time and the energy consumption effectively.

show abstract

“…For each pair (i, j), the optimal energy cost C[ i , j] is computed (instructions [11][12][13][14][15][16][17][18][19] as the minimum between the energy consumed in the monolithic case, and The conditional instruction 13 eliminates the solutions exceeding M number of banks. Arbitrarily fine partitioning is prevented since an excessively large number of small banks is area inefficient, imposing a severe wiring overhead, which also tends to increase communication power and decrease performance.…”

Section: Lattice-based Dynamic Programming Algorithmmentioning

confidence: 99%

“…In [6], the cost function was shown to exhibit properties that allow to apply a dynamic programming paradigm. A leakage-aware approach, based on traces of memory accesses, takes into account that putting a memory block into the dormant state should be done only if the cost of energy overhead and decrease of performance can be amortized [15,16].…”

Section: Introductionmentioning

confidence: 99%

Energy-aware memory management for embedded multidimensional signal processing applications

et al. 2016

View full text Add to dashboard Cite

In real-time data-intensive multimedia processing applications, data transfer and storage significantly influence, if not dominate, all the major cost parameters of the design space-namely energy consumption, performance, and chip area. This paper presents an electronic design automation (EDA) methodology for the high-level design of hierarchical memory architectures in embedded data-intensive applications, mainly in the area of multidimensional signal processing. Different from the previous works, the problems of data assignment to the memory layers, of mapping the signals into the physical memories, and of banking the on-chip memory are addressed in a consistent way, based on the same formal model. This memory management framework employs techniques specific to the integral polyhedra based dependence analysis. The main design target is the reduction of the static and dynamic energy consumption in the hierarchical memory subsystem.

show abstract

Architectural Leakage-Aware Management of Partitioned Scratchpad Memories

Cited by 15 publications

References 11 publications

Reducing leakage power with BTB access prediction

Reducing leakage power with BTB access prediction

Scratchpad memory based power efficient optimization for MPSoC

Energy-aware memory management for embedded multidimensional signal processing applications

Contact Info

Product

Resources

About