Architectural framework for supporting operating system survivability

Jiang, Xiaowei; Solihin, Yan

doi:10.1109/hpca.2011.5749751

Cited by 3 publications

(3 citation statements)

References 28 publications

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“…LLC side channel attack on the cloud environment happens when the virtual memory is shared among several users. Ghost (General hardware-oriented system transfer) is disk cloning and a backup tool used in the cloud computing environment and the Ghost memory should not be shared with the OS compromised system [9]. If the cache lines of physical memory are mapped to the ghost memory, then the operations like read or eviction should not happen to that memory.…”

Section: Last Level Cache Side Channelsmentioning

confidence: 99%

Detecting Cache-Based Side Channel Attacks in IaaS using Enhanced Algorithm

2019

IJITEE

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The Connectivity of the information among people throughout the world is made possible through computers and smart devices connected over the internet. The economic related transactions also happen over the network which needs a secured transaction medium. Therefore, lots of intrusion detection and prevention systems are implemented in order to reduce the impact of the attack. But every year the impact of attack over the shared VMs is being dramatically increased. The economic transactions occur with the help of web applications and they are divided into browser-side and server-side components. One of the major services provided by the cloud environment is Infrastructure-asa-Service in which the virtual machines are used to provide the shared services to the multiple users. Though the VMs are secured by implementing the various security algorithms, one of the attacks, Side-channel attack, uses the leaked information acquired from the implementation of hardware component. Cache-based side channel attack is the serious attack, which tries to steal the sensitive information like credit card details, password, medical related details, etc., by establishing various algorithms like PRIME+PROBE, FLUSH+RELOAD, FLUSH+FLUSH, etc.,. The VM does speculative execution for improving the CPU performance, thus resulting in a scenario which allows the user to access the sensitive data on the cache line. So in this paper the environment is set up with 5 various scenarios with the combinations consisting of attack, no-attack, Full load, Average load and no-load. The Hardware Performance Counters (HPC) is used along with Intel CMT to monitor and distinguish the attacker VM, thus increasing the detection accuracy and reducing the system overhead.

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Section: Last Level Cache Side Channelsmentioning

confidence: 99%

Detecting Cache-Based Side Channel Attacks in IaaS using Enhanced Algorithm

2019

IJITEE

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“…Net savings in silicon will be reduced on-die SRAM minus the extra logic for buffer management, and cost for increasing the system interconnect width and cache port should they become necessary. Two important aspects that we leave for future work are security [17,49] and power implications of BiC…”

Section: Key Memory Movement When Receiving a Packet With On-chip Nmentioning

confidence: 99%

Cost-effectively offering private buffers in SoCs and CMPs

Fang

Zhao

Iyer

et al. 2011

Proceedings of the International Conference on Supercomputing

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High performance SoCs and CMPs integrate multiple cores and hardware accelerators such as network interface devices and speech recognition engines. Cores make use of SRAM organized as a cache. Accelerators make use of SRAM as special-purpose storage such as FIFOs, scratchpad memory, or other forms of private buffers. Dedicated private buffers provide benefits such as deterministic access, but are highly area inefficient due to the lower average utilization of the total available storage. We propose Buffer-integrated-Caching (BiC), which integrates private buffers and traditional caches into a single shared SRAM block. Much like shared caches improve SRAM utilization on CMPs, the BiC architecture generalizes this advantage for a heterogeneous mix of cores and accelerators in future SoCs and CMPs. We demonstrate cost-effectiveness of the BiC using SoC-based low-power servers and CMP-based servers with on-chip NIC. We show that with a small extra area added to the baseline cache, BiC removes the need for large, dedicated SRAMs, with minimal performance impact.

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“…However, the availability of off-chip bandwidth is only projected to grow at a much lower 15% annual rate, due to the limitations in pin density and power consumption [13]. This discrepancy leads to a problem called the bandwidth wall, where system performance is increasingly limited by the availability of off-chip bandwidth [7,14,15,16,17,18,22,23,30]. Hence, the demand for efficient use of off-chip bandwidth is tremendous and increasing.…”

Section: Introductionmentioning

confidence: 99%

Studying the impact of hardware prefetching and bandwidth partitioning in chip-multiprocessors

Liu

Solihin

2011

Proceedings of the ACM SIGMETRICS Joint International Conference on Measurement and Modeling of Computer Systems

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Modern high performance microprocessors widely employ hardware prefetching technique to hide long memory access latency. While very useful, hardware prefetching tends to aggravate the bandwidth wall, a problem where system performance is increasingly limited by the availability of the off-chip pin bandwidth in Chip Multi-Processors (CMPs).In this paper, we propose an analytical model-based study to investigate how hardware prefetching and memory bandwidth partitioning impact CMP system performance and how they interact. The model includes a composite prefetching metric that can help determine under which conditions prefetching can improve system performance, a bandwidth partitioning model that takes into account prefetching effects, and a derivation of the weighted speedupoptimum bandwidth partition sizes for different cores. Through model-driven case studies, we find several interesting observations that can be valuable for future CMP system design and optimization. We also explore simulation-based empirical evaluation to validate the observations and show that maximum system performance can be achieved by selective prefetching, guided by the composite prefetching metric, coupled with dynamic bandwidth partitioning.

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Architectural framework for supporting operating system survivability

Cited by 3 publications

References 28 publications

Detecting Cache-Based Side Channel Attacks in IaaS using Enhanced Algorithm

Detecting Cache-Based Side Channel Attacks in IaaS using Enhanced Algorithm

Cost-effectively offering private buffers in SoCs and CMPs

Studying the impact of hardware prefetching and bandwidth partitioning in chip-multiprocessors

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