Studying the impact of hardware prefetching and bandwidth partitioning in chip-multiprocessors

Liu, Fang; Solihin, Yan

doi:10.1145/1993744.1993749

Cited by 32 publications

(10 citation statements)

References 38 publications

(63 reference statements)

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“…A major limitation of cache bypassing technique is, it could prove to be partially benefited as it already pollutes the cache, by replacing data once. Liu et al (2008), and Liu and Solihin (2011) aim to predict deadblocks based on bursts of accesses to a cache block rather than individual accesses. The work investigates references made to a cache line when it moves from MRU position to LRU position to predict deadblocks.…”

Section: Deadblock Predictions To Reduce Cache Contentionmentioning

confidence: 99%

“…• Prefetching and bandwidth partitioning: According to Moore's law, the quantity of transistors is doubling rapidly as compared to bandwidth which hardly grows 10 to 15%, it becomes challenging for bandwidth to handle the pressure due to increasing cores and leads to the âŁ˜bandwidth wall' crises. Exploiting the combined effect of prefetching and bandwidth partitioning Liu and Solihin (2011) propose a scheme that investigates prefetching conditions and describes a bandwidth partitioning policy coupled with the effects due to prefetching.…”

Section: Studying Impact Of Prefetching With Other Shared Resourcesmentioning

confidence: 99%

A review on shared resource contention in multicores and its mitigating techniques

Jain

Surve

2020

IJHPSA

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Chip multiprocessor (CMP) systems have become inevitable to meet high computing demands. In such systems sharing of resources is imperative for better resource utilisation. The challenge arises when various application programs running on neighbouring cores compete for these resources concurrently and introduce contention. We aim to present in a simple, lucid and captivating manner a review of previous work on contention in multicores due to various shared resources like shared caches, main memory, memory bus bandwidth, prefetchers etc. The work investigates key ideas proposed by the research community to alleviate resource contention due to these various resources, under a single umbrella. The prime objective of the study is to throw light upon the fact that, alone a single shared component is not a dominant reason for performance degradation in CMPs, rather all elements in the memory hierarchy introduce resource contention thereby affecting performance cumulatively. The work presented would assist novice readers, researchers and academicians to further serve to propose optimal policies to address contention in designing multicore applications, considering the overall impact of these resources on the performance of multicore systems.

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“…Regarding the NoC, some interesting approaches [21,22] implement virtual channels and dynamically adjust the priority between regular and prefetch requests coming from multiple cores. With respect to memory controller policies, recent proposals [23,24,25] have also focused on multicores. These policies take into account the prefetcher performance to dynamically select the priority of both regular and prefetch requests.…”

Section: Related Workmentioning

confidence: 99%

Efficient selective multicore prefetching under limited memory bandwidth

Selfa

Sahuquillo

Gomez

et al. 2018

Journal of Parallel and Distributed Computing

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Current multicore systems implement multiple hardware prefetchers to tolerate long main memory latencies. However, memory bandwidth is a scarce shared resource which becomes critical with the increasing core count. To deal with this fact, recent works have focused on adaptive prefetchers, which control the prefetcher aggressiveness to regulate the main memory bandwidth consumption. Nevertheless, in limited bandwidth machines or under memory-hungry workloads, keeping active the prefetcher can damage the system performance and increase energy consumption. This paper introduces selective prefetching, where individual prefetchers are activated or deactivated to improve both main memory energy and performance, and proposes ADP, a prefetcher that deactivates local prefetchers in some cores when they present low performance and co-runners need additional bandwidth. Based on heuristics, an individual prefetcher is reactivated when performance enhancements are foreseen. Compared to a state-of-the-art adaptive prefetcher, ADP provides both performance and energy enhancements in limited memory bandwidth.

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“…characterize cache pollution in the real system and propose a prefetch manager that controls the aggressiveness at runtime. Liu and Solihin [2011] propose an analytical model to study the interaction of hardware prefetching and bandwidth partitioning on a multicore system.…”

Section: Caffeine On Ghb Prefetchermentioning

confidence: 99%

Caffeine

Panda

Balachandran

2015

ACM Trans. Archit. Code Optim.

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Aggressive prefetching improves system performance by hiding and tolerating off-chip memory latency. However, on a multicore system, prefetchers of different cores contend for shared resources and aggressive prefetching can degrade the overall system performance. The role of a prefetcher aggressiveness engine is to select appropriate aggressiveness levels for each prefetcher such that shared resource contention caused by prefetchers is reduced, thereby improving system performance. State-of-the-art prefetcher aggressiveness engines monitor metrics such as prefetch accuracy, bandwidth consumption, and last-level cache pollution. They use carefully tuned thresholds for these metrics, and when the thresholds are crossed, they trigger aggressiveness control measures. These engines have three major shortcomings: (1) thresholds are dependent on the system configuration (cache size, DRAM scheduling policy, and cache replacement policy) and have to be tuned appropriately, (2) there is no single threshold that works well across all the workloads, and (3) thresholds are oblivious to the phase change of applications. To overcome these shortcomings, we propose CAFFEINE, a model-based approach that analyzes the effectiveness of a prefetcher and uses a metric called net utility to control the aggressiveness. Our metric provides net processor cycles saved because of prefetching by approximating the cycles saved across the memory subsystem, from last-level cache to DRAM. We evaluate CAFFEINE across a wide range of workloads and compare it with the state-of-theart prefetcher aggressiveness engine. Experimental results demonstrate that, on average (geomean), CAFFEINE achieves 9.5% (as much as 38.29%) and 11% (as much as 20.7%) better performance than the best-performing aggressiveness engine for four-core and eight-core systems, respectively.

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“…An aggressive hardware prefetcher may completely hide the latency of off-chip memory accesses. However, it may cause severe interference at the shared resources (last level cache and memory bandwidth) of a multi-core system [Ebrahimi et al 2009[Ebrahimi et al , 2011Wu et al 2011;Seshadri et al 2015;Panda and Balachandran 2015;Jimenez et al 2015;Panda 2016;Lee et al 2008;Liu and Solihin 2011;Bitirgen et al 2008]. To manage prefetching in multi-core systems, prior studies [Srinath et al 2007;Ebrahimi et al 2009Ebrahimi et al , 2011Panda and Balachandran 2015;Panda 2016] have been proposed to dynamically control (also known as throttling) the prefetcher aggressiveness by adjusting the prefetcher-configuration at runtime.…”

Section: Introductionmentioning

confidence: 99%

Band-Pass Prefetching

Sridharan

Panda

Seznec

2017

ACM Trans. Archit. Code Optim.

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In multi-core systems, an application's prefetcher can interfere with the memory requests of other applications using the shared resources, such as last level cache and memory bandwidth. In order to minimize prefetcher-caused interference, prior mechanisms have been proposed to dynamically control prefetcher aggressiveness at runtime. These mechanisms use several parameters to capture prefetch usefulness as well as prefetcher-caused interference, performing aggressive control decisions. However, these mechanisms do not capture the actual interference at the shared resources and most often lead to incorrect aggressiveness control decisions. Therefore, prior works leave scope for performance improvement. Toward this end, we propose a solution to manage prefetching in multicore systems. In particular, we make two fundamental observations: First, a positive correlation exists between the accuracy of a prefetcher and the amount of prefetch requests it generates relative to an application's total (demand and prefetch) requests. Second, a strong positive correlation exists between the ratio of total prefetch to demand requests and the ratio of average last level cache miss service times of demand to prefetch requests. In this article, we propose Band-pass prefetching that builds on those two observations, a simple and low-overhead mechanism to effectively manage prefetchers in multicore systems. Our solution consists of local and global prefetcher aggressiveness control components, which altogether, control the flow of prefetch requests between a range of prefetch to demand requests ratios. From our experiments on 16-core multi-programmed workloads, on systems using stream prefetching, we observe that Band-pass prefetching achieves 12.4% (geometric-mean) improvement on harmonic speedup over the baseline that implements no prefetching, while aggressive prefetching without prefetcher aggressiveness control and state-of-the-art HPAC, P-FST, and CAFFEINE achieve 8.2%, 8.4%, 1.4%, and 9.7%, respectively. Further evaluation of the proposed Band-pass prefetching mechanism on systems using AMPM prefetcher shows similar performance trends. For a 16-core system, Band-pass prefetching requires only a modest hardware cost of 239 bytes.

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Studying the impact of hardware prefetching and bandwidth partitioning in chip-multiprocessors

Cited by 32 publications

References 38 publications

A review on shared resource contention in multicores and its mitigating techniques

Efficient selective multicore prefetching under limited memory bandwidth

Caffeine

Band-Pass Prefetching

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