Architecting advanced technologies for 14nm and beyond with 3D FinFET transistors for the future SoC applications

Keshavarzi, Ali; Somasekhar, Dinesh; Rashed, M.; Ahmed, Shibly; Maitra, K.; Miller, Robert J.; Knorr, A.; Cho, Jin; Augur, Rod; Banna, Srinivasa; Shaw, C-H.; Halliyal, A.; Schroeder, Uwe; Wei, A.; Egley, James; Korablev, K.; Luning, S.; Lin, Ming-Ren; Venkatesan, S.; Kengeri, Subramani; Bartlett, Greg

doi:10.1109/iedm.2011.6131485

Cited by 18 publications

(8 citation statements)

References 2 publications

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“…Both can be mitigated using 3D structures that present a better electrostatic control of the conduction over the device channel. In this scenario, FinFETs appeared as a suitable FET device, which is currently the basic building block for high volume manufacturing of integrated circuits [1]. Nevertheless, beyond 10 nm, an alternative FET architecture is the vertical nanowire, which can provide improved performance thanks to its full gate-all-around (GAA) structure and smaller footprint.…”

Section: Introductionmentioning

confidence: 99%

Exploring Strategies to Contact 3D Nano-Pillars

et al. 2020

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This contribution explores different strategies to electrically contact vertical pillars with diameters less than 100 nm. Two process strategies have been defined, the first based on Atomic Force Microscope (AFM) indentation and the second based on planarization and reactive ion etching (RIE). We have demonstrated that both proposals provide suitable contacts. The results help to conclude that the most feasible strategy to be implementable is the one using planarization and reactive ion etching since it is more suitable for parallel and/or high-volume manufacturing processing.

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Section: Introductionmentioning

confidence: 99%

Exploring Strategies to Contact 3D Nano-Pillars

et al. 2020

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“…Invented in 1992, the ion-cut process has been developed into a mature manufacturing technology for silicon on insulator (SOI) materials and many applications in sensors, optoelectronics, and microelectronics. − However, this process always requires the addition of a polish-to-thin step to remove the damaged region caused by layer-splitting and to thin the transferred layer (usually at several hundred nanometers) to a thickness of less than 100 nm.…”

Section: Introductionmentioning

confidence: 99%

Rapid Fabrication of 100 nm or Thinner Fully Depleted Silicon-on-Insulator Materials for Ultralow Energy Consumption

Lee

Huang

et al. 2018

ACS Appl. Nano Mater.

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The fully depleted silicon-on-insulator (FD-SOI) wafer is the core material of the FD-SOI technology used for manufacturing the applications with ultralow energy consumption for internet of things, artificial intelligence, automotive, and wearable devices. Ion-cut process is the main technology to fabricate FD-SOI wafers. After ion cutting, the silicon layer transferred on the insulator includes a spongelike damaged layer. Therefore, it must contain a thinning buffer layer with a thickness more than 150 nm to remove the damaged layer by a polishing step. The requirement of the additional buffer layer makes the direct fabrication of a less than 100 nm thick SOI layer from the as-split status impossible. Here, we develop a process based on solid-phase epitaxial growth (SPEG) technique, abandoning the polishing step, and thus achieve a one-step fabrication of FD-SOI substrate. First, inducing amorphization of an SOI layer via blistering supersaturated hydrogen ions through microwaving fully consumes the possible stable defect clusters. Next, using SPEG technique catalyzed by surrounding hydrogen ions restores the amorphized SOI layer to the initial crystalline structure. To approach the purpose, a silicon (Si)-clad layer deposited on the oxidized surface was used. The Si-clad layer has two functions promoting the success of SPEG processing. It acts as a filter to prevent co-implanted impurities in the silicon layer to avoid the occurrence of crystal segregation during recrystallization. It also serves as a sacrificial layer to bring the split location close to the implant peak causing the hydrogen concentration in the entire SOI layer in supersaturation. When amorphizing this layer, an undamaged crystalline layer is retained at the interface of the SiO2/Si as a seed layer to promote the regrowth of a perfect SOI layer in a argon-annealing step. By integrating with the ion-shower implantation used in flat-panel display manufacturing, the technology can fabricate the next generation of larger SOI wafers without the need to upgrade the ion implanter.

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“…Next, S/D selective epitaxial growth is performed, followed by poly gate removal and metal gate deposition, and, finally, the contact vias are formed. These experiments were carried out on a state of the art 14nm-node [4]. A raised S/D is used for N and P-type.…”

Section: Introductionmentioning

confidence: 99%

Advanced TCAD for predictive FinFETs Vth mismatch using full 3D process/device simulation

Bazizi

Zaka

Herrmann

et al. 2014

2014 44th European Solid State Device Research Conference (ESSDERC)

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Predictive TCAD tool is crucial for several reasons such as to provide pre-silicon data, shorten the technology development cycle and reduce the fabrication cost. In this paper, advanced 3D TCAD process and device simulations is used to gain physical understanding and to optimize the performance/variability of bulk-FinFETs. For the first time, the full FinFET process flow simulation was performed using diffusion, activation and segregation models identical to those used in planar nodes. In this work a wide range of implantation and anneal splits is used to demonstrate the 3D simulation accuracy. After achieving good agreement with experiments in terms of Vth and Ion/Ioff, considering lateral dopant diffusion and activation, the simulation was used to investigate SRAM random doping fluctuation RDF.

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Architecting advanced technologies for 14nm and beyond with 3D FinFET transistors for the future SoC applications

Cited by 18 publications

References 2 publications

Exploring Strategies to Contact 3D Nano-Pillars

Exploring Strategies to Contact 3D Nano-Pillars

Rapid Fabrication of 100 nm or Thinner Fully Depleted Silicon-on-Insulator Materials for Ultralow Energy Consumption

Advanced TCAD for predictive FinFETs Vth mismatch using full 3D process/device simulation

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