Architecting 3-D integrated circuit fabric with intrinsic thermal management features

Rahman, Mostafizur; Khasanvis, Santosh; Shi, Jiajun; Li, Mingyu; Moritz, Csaba Andras

doi:10.1109/nanoarch.2015.7180605

Cited by 15 publications

(6 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…All active components/structures described in this work rely on multi-layer material deposition techniques which have lower cost, and can be controlled to few Angstrom's precision. Manufacturing pathway for S3DC and experimental demonstrations are discussed in [9]. Fig.…”

Section: Overview Of Skybridgementioning

confidence: 99%

“…Skybridge [7] is a truly fine-grained 3D IC fabric that uses vertically-stacked gates interconnected in 3D on a template of vertical nanowires to yield orders of magnitude benefits over 2D CMOS. Core fabric aspects including device, circuit-style, connectivity [8], thermal management [9] and pathway of manufacturing [10] are co-architected for 3D compatibility. Input/output pins for each vertically-composed gate have multiple points of access both horizontally and vertically which can be reached through architected routing components, as opposed to T-MI which limits pin-access to a 2D plane and relies on conventional routing schemes.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Power-delivery network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS

Shi

Moritz

2017

2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

Self Cite

View full text Add to dashboard Cite

Conventional 2D CMOS technology is reaching fundamental scaling limits, and interconnect bottleneck is dominating integrated circuit (IC) power and performance. While 3D IC technologies using Through Silicon Via or Monolithic Inter-layer Via alleviate some of these challenges, they follow a similar layout and routing mindset as 2D CMOS. This is insufficient to address routing requirements in high-density 3D ICs and even causes severe routing congestion at large-scale designs, limiting their benefits and scalability. Skybridge is a recently proposed fine-grained 3D IC fabric relying on vertical nanowires that presents a paradigm shift for scaling, while addressing associated 3D connectivity and manufacturability challenges. Skybridge's core fabric components enable a new 3D IC design approach with vertically-composed logic gates, and provide a greater degree of routing flexibility compared to conventional 2D and 3D ICs leading to much larger benefits and future scalability. In this paper, we present a methodology using relevant metrics to evaluate and quantify the benefits of Skybridge vs. state-of-the-art transistor-level monolithic 3D IC (T-MI) and 2Din terms of routability and its impact on large-scale circuits. This is enabled by a new device-to-system design flow with commercial CAD tools that we developed for large-scale Skybridge IC designs in 16nm node. Evaluation for standard benchmark circuits shows that Skybridge yields up to 1.6x lower routing demand against T-MI with no routing congestion (routing demand to resource ratio < 1) at all metal layers. This 3D routability in conjunction with compact vertical gate design in Skybridge translate into benefits of up to 3x lower power and 11x higher density over 2D CMOS, while TLM-3DIC approach only has up to 22% power saving and 2x density improvement over 2D CMOS.

show abstract

Section: Overview Of Skybridgementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Power-delivery network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS

Shi

Moritz

2017

2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

Self Cite

View full text Add to dashboard Cite

show abstract

“…In S3DC, we envision that heat extraction is added during the circuit synthesis / design stage through CAD. Heat extraction components, including Heat Extraction Junctions (HEJs) and Heat Dissipating Power Pillars (HDPPs), are specifically designed for S3DC following design principles as in [7] to provide distributed heat dissipation paths. HEJs are specialized junctions that extract heat from the hot spot on a nanowire without affecting circuit function; the extracted heat is carried by Heat Extraction Bridges and is dissipated to the bulk silicon substrate through HDPPs, which are larger dimension pillars.…”

Section: S3dc Heat Managementmentioning

confidence: 99%

“…The S3DC's thermal management was evaluated with analogous analysis in the electrical domain [13]. Equivalent thermal resistance models for transistors and logicimplementing nanowires following similar principles in [7] have been developed. Next, we built benchmark circuits in scenarios when two gates with various numbers of transistors are stacked on one nanowire, and completed HSPICE simulations for worst-case heat dissipating scenarios when the transistors generate most total heat.…”

Section: A Thermal Management Evaluationmentioning

confidence: 99%

Skybridge-3D-CMOS: A Vertically-Composed Fine-Grained 3D CMOS Integrated Circuit Technology

Shi

Rahman

et al. 2016

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

Self Cite

View full text Add to dashboard Cite

Abstract-Parallel and monolithic 3D integration directions offer pathways to realize 3D integrated circuits (ICs) but still lead to layer-by-layer implementations, each functional layer being composed in 2D first. This mindset causes challenging connectivity, routing and layer alignment between layers when connected in 3D, with a routing access that can be even worse than 2D CMOS, which fundamentally limits their potential. To fully exploit the opportunities in the third dimension, we propose Skybridge-3D-CMOS TM (S3DC), a fine-grained 3D integration approach that is directly composed in 3D, utilizing the vertical dimension vs. using a layer-by-layer assembly mindset. S3DC uses a novel wafer fabric creation with direct 3D design and connectivity in the vertical dimension. It builds on a uniform vertical nanowire template that is processed as a single wafer; it incorporates specifically architected structures for realizing devices, circuits, and heat management directly in 3D. Novel 3D interconnect concepts, including within the silicon layers, enable significantly improved routing flexibility in all three dimensions and a high-density 3D design paradigm overall. Intrinsic components for fabric-level 3D heat management are introduced. Extensive bottom-up simulations and experiments have been presented to validate the key fabric-enabling concepts. Evaluation results indicate up to 40x density and 10x performance-per-watt benefits against conventional 16-nm CMOS for the circuits studied; benefits are also at least an order of magnitude beyond what was shown to be possible with other 3D directions.

show abstract

“…The other way is through Through Silicon Vias (TSVs) to improve the heat dissipation in overheated regions, either by placing more signal TSVs at regions with higher temperatures [18] or by inserting additional dummy TSVs that are only for thermal purposes (Thermal TSVs)this is to increase the number of thermal paths between tiers [17]. In S3DC we have proposed 3-D thermal management fabric components that directly support thermal management at a fine granularity [22]. These are specially architected fabric components; they are also integrated as intrinsic parts of the circuits during an electrical-thermal circuit co-design CAD flow.…”

Section: Introductionmentioning

confidence: 99%

Machine Learning Based Thermal Evaluation for Vertically-Composed Fine-Grained 3D CMOS

Li¹,

Kulkarni²,

Bhat³

et al. 2022

Preprint

View full text Add to dashboard Cite

<p>Thermal management in 3D integrated circuits is a critical challenge due to their high computational density. Heat dissipation paths from top circuit layers through bottom layers to substrate are heavily constraining heat extraction. Various thermal management frameworks have been proposed to address thermal issues in different granularities. All these frameworks require a thermal evaluation stage that characterizes the thermal profile of large designs with fast runtime. In this work, we present a machine learning based thermal evaluation method that predicts all standard cell temperatures based on features extracted from circuit CAD files. We have built thermal resistance networks for 10 benchmark circuits. We performed simulations to achieve the thermal data, and trained the thermal model with the data. The model is highly accurate and can identify all over-heated cells that need to be thermally-optimized. Runtime overhead is minimal. For a 435k-cell SPARC T2 core, the runtime for predicting all cell temperatures is as small as 3.12s, which is negligible compared to the runtime of other physical design stages. </p>

show abstract

Architecting 3-D integrated circuit fabric with intrinsic thermal management features

Cited by 15 publications

References 14 publications

Power-delivery network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS

Power-delivery network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS

Skybridge-3D-CMOS: A Vertically-Composed Fine-Grained 3D CMOS Integrated Circuit Technology

Machine Learning Based Thermal Evaluation for Vertically-Composed Fine-Grained 3D CMOS

Contact Info

Product

Resources

About