ArchExplorer for Automatic Design Space Exploration

Desmet, Veerle; Girbal, Sylvain; Ramírez, Alex; Temam, Olivier; Vega, Augusto

doi:10.1109/mm.2010.76

Cited by 9 publications

(5 citation statements)

References 23 publications

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“…The ArchExplorer [6] framework is a website that serves as an implementation platform for design space exploration. The user can choose the simulator and upload it to the platform.…”

Section: Related Workmentioning

confidence: 99%

A-DECA: An Automated Design Space Exploration Approach for Computing Architectures to Develop Efficient High-Performance Many-Core Processors

Zaourar,

Chillet,

Philippe

2023

2023 26th Euromicro Conference on Digital System Design (DSD)

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High-performance many-core processors have complex computing architectures with many design parameters related to different levels (CPU macro/micro-architecture, interconnect, memory, specific accelerators, etc.). Design Space Exploration (DSE) is key to tackle the challenges related to the design of such processors, especially in the early stages. This work introduces A-DECA, a highly modular DSE approach for automating the exploration of design parameters. A-DECA combines simulators, models, and exploration strategies to derive relevant objective estimations while preserving a reasonable execution time. Thus, it provides a full methodology enabling the exploration of the design space in an easy-to-use, automatic, and effective way. A-DECA is evaluated in the context of next-generation HPC processors with various applications. We combine simulation tools and analytical formulations to assess PPA (Performance, Power, and Area). Based on an efficient implementation of a multi-objective genetic algorithm for the exploration strategy, current results show a great reduction of design space optimization by around 30% compared to the initial population. A-DECA optimizes the objectives and automatically returns a set of configurations with different characteristics allowing the architect to choose the best design according to the application context.

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“…The ArchExplorer [6] framework is a website that serves as an implementation platform for design space exploration. The user can choose the simulator and upload it to the platform.…”

Section: Related Workmentioning

confidence: 99%

A-DECA: An Automated Design Space Exploration Approach for Computing Architectures to Develop Efficient High-Performance Many-Core Processors

Zaourar,

Chillet,

Philippe

2023

2023 26th Euromicro Conference on Digital System Design (DSD)

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“…They use different heuristics to find the optimal solutions for a given hardware architecture. Just to name some of them: FADSE (multi-objective automatic design space exploration framework that is very versatile and uses state-of-the-art multi-objective optimization algorithms), Archexplorer [6] (a Web-based permanent and open designspace exploration framework that lets researchers compare their designs against others), Multicube Explorer [7] (an interactive open-source framework to enable the designer to automatically explore a design space of configurations for a parameterized architecture), Magellan [8] (a Search and Machine Learning-based Framework for Fast Multi-core Design Space Exploration and Optimization), NASA [9] (a Generic Infrastructure for System-level MP-SoC Design Space Exploration), SystemCoDesigner [10] (a novel SystemC-based ESL tool to automatically optimize a hardware/software SoC -System on Chip -implementation with respect to several objectives), HArtes [11] (holistic approach to reconfigurable real-time embedded systems).…”

Section: Related Wordmentioning

confidence: 99%

Multi-objective hardware-software co-optimization for the SNIPER multi-core simulator

Chis

Vintan

2014

2014 IEEE 10th International Conference on Intelligent Computer Communication and Processing (ICCP)

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Modern complex microarchitectures with multicore systems like CPUs, APUs (accelerated processing units) and GPUs require hundreds or thousands of hardware parameters to be fine-tuned to get the best results regarding different objectives like: performance, hardware complexity (integration area), power consumption, temperature, etc. These are only a few of the objectives needed to be taken into consideration when designing a new multicore system. Exploring this huge design space requires special tools like automatic design space exploration frameworks to optimize the hardware parameters. Although the microarchitecture might be very complex, the performance of the applications is also highly dependent on the degree of software optimization. This adds a new challenge to the DSE process. In this paper, using the multi-objective design space exploration tool FADSE, we tried to optimize the hardware and software parameters of the multicore SNIPER simulator running SPLASH-2 benchmarks suite. We optimized the hardware parameters (nr cores, cache sizes, cache associativity, etc.) and software parameters (GCC optimizations, threads, and scheduler) values that have been varied during the DSE process and shown the impact of these parameters on the optimization's multi-objectives (performance, area and power consumption). Furthermore, for the best found Pareto configurations the temperatures will be computed so that in the end we will have a 4-dimensional objective space.

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“…Recently, the Archexplorer [Desmet et al 2010] and the Multicube [Silvano et al 2010] frameworks have been presented for automatic DSE, both targeting the microarchitecture level from a different point of view. Archexplorer is a Web-based framework that focuses on the integration of various micro-architectural components (i.e., cache mechanisms) in a unified simulation framework.…”

Section: Related Workmentioning

confidence: 99%

“…Archexplorer is a Web-based framework that focuses on the integration of various micro-architectural components (i.e., cache mechanisms) in a unified simulation framework. It explores the design space generated from the various component models using a variant of genetic algorithm [Desmet et al 2010]. Multicube explorer is a simulator-agnostic framework and focuses on the analytical modeling of the design space, offering a large set of multi-objective optimization algorithms [Silvano et al 2010].…”

Section: Related Workmentioning

confidence: 99%

Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs

Xydis

Pekmestzi

Soudris

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

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Design space exploration during high-level synthesis targets the computation of those design solutions which form optimal trade-off points. This quest for optimal trade-offs has been focused on studying the impact of various architectural-level parameters during high-level synthesis algorithms, silently neglecting the tradeoffs produced from the combined impact of behavioral-level together with architectural-level parameters. We propose a novel design space, exploration methodology that studies an extended instance of the solution space considering the effects of combining compiler-and architectural-level transformations. It is shown that exploring the design space in a global manner reveals new trade-off points, thus shifting towards higher quality design solutions. We use a combination of upper-bounding conditions together with gradient-based heuristic pruning to efficiently traverse the extended search space. Our exploration framework delivers significant quality improvements without compromising the optimality (Pareto accuracy) of the discovered solutions, together with significant runtime reductions compared to exploring exhaustively the solution space at every allocation scenario.

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ArchExplorer for Automatic Design Space Exploration

Cited by 9 publications

References 23 publications

A-DECA: An Automated Design Space Exploration Approach for Computing Architectures to Develop Efficient High-Performance Many-Core Processors

A-DECA: An Automated Design Space Exploration Approach for Computing Architectures to Develop Efficient High-Performance Many-Core Processors

Multi-objective hardware-software co-optimization for the SNIPER multi-core simulator

Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs

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