Multi-objective hardware-software co-optimization for the SNIPER multi-core simulator

Chis, Radu; Vintan, Lucian

doi:10.1109/iccp.2014.6936772

Cited by 3 publications

(3 citation statements)

References 15 publications

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“…The algorithm designed for the Fat-Tree topology is subjected to simulation using the Sniper simulator. This simulator, renowned for its high-performance capabilities, operates as a parallel and cycle-accurate tool specially crafted for the next-generation simulation needs [26,27]. Within this simulation environment, a diverse array of computing scenarios can be explored, including both homogeneous and heterogeneous multicore architectures.…”

Section: Experimental Setup and Results Analysismentioning

confidence: 99%

An Energy-Efficient Routing Protocol for a Modified Fat-Tree Topology in System-on-Chip Design

Yadav,

Ahmed,

Ambudkar

et al. 2023

MMEP

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The rapid evolution of integration technology has significantly influenced System-on-Chip (SoC) design, characterized by the unprecedented integration of numerous functional modules onto ever-shrinking chips. Consequently, facilitating robust communication between these burgeoning modules has become critical to optimizing system functionality and performance. Traditional Bus architecture, however, proves inadequate in realizing this goal. To circumvent these communication impediments, mesh and torus interconnected architectures have been proposed, with cores interconnected within a single chip using diverse routing strategies for seamless operation. This study investigates a deterministic, deadlock-free routing protocol for a modified Fat-Tree topology that incorporates a core module at the intermediate level.Utilizing the Sniper simulator environment for evaluation, it is demonstrated that the proposed protocol surpasses the X-Y routing method used in both mesh and torus topologies in terms of power efficiency and throughput. The results show a 4%-8% reduction in power consumption compared to other approaches, indicating the superior efficacy of the proposed method.

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Section: Experimental Setup and Results Analysismentioning

confidence: 99%

An Energy-Efficient Routing Protocol for a Modified Fat-Tree Topology in System-on-Chip Design

Yadav,

Ahmed,

Ambudkar

et al. 2023

MMEP

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“…The critical feature of the sniper simulator is has a core model that depends on the period simulation [10]. The main reason which makes the simulator be faster development and evaluation times by using intervals which mean 'jumping' between miss events [17].…”

Section: B Sniper Simulatormentioning

confidence: 99%

An Overview of Cycle-Accurate, Event-Driven and Full Systems Simulators for Chip-Multiprocessors

Janabi¹,

Agyeman²

2019

IJCTE

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Due to the growing number of Chip-Multiprocessors, the researchers have proposed new designs and architectures. So, there is a constant need to know the most accurate simulators used in this scope, which should be used to identify their outcomes. Computer System Architecture (CSA) simulators are usually used to validate the designs, architectures that new discovered and developments. This paper is to provide an overview and insight into the most critical simulations used in Computer System Architecture and possible standards that distinguish simulators from the other. The essential aspects and parameters that determine these simulators are accuracy, speed, performance, flexibility, and functionality as well. Cycle-Accurate, Event-Driven and Full Systems Simulators of CSA, this taxonomy of simulators that w discusses in this paper.

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“…It is a high speed simulator for x86 architecture. SNIPER has been developed for calculating the performance of a processor, the energy consumed by the processor and the integration area [15]. SNIPER has been extensively exploited for obtaining results.…”

Section: Sniper Simulatormentioning

confidence: 99%

Towards Multi-objective Optimization of Automatic Design Space Exploration for Computer Architecture through Hyper-heuristic

Latif

Ismail

2019

Eng. Technol. Appl. Sci. Res.

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Multi-objective optimization is an NP-hard problem. ADSE (automatic design space exploration) using heuristics has been proved to be an appropriate method in resolving this problem. This paper presents a hyper-heuristic technique to solve the DSE issue in computer architecture. Two algorithms are proposed. A hyper-heuristic layer has been added to the FADSE (framework for automatic design space exploration) and relevant algorithms have been implemented. The benefits of already existing multi-objective algorithms have been joined in order to strengthen the proposed algorithms. The proposed algorithms, namely RRSNS (round-robin scheduling NSGA-II and SPEA2) and RSNS (random scheduling NSGA-II and SPEA2) have been evaluated for the ADSE problem. The results have been compared with NSGA-II and SPEA2 algorithms. Results show that the proposed methodologies give competitive outcomes in comparison with NSGA-II and SPEA2.

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Multi-objective hardware-software co-optimization for the SNIPER multi-core simulator

Cited by 3 publications

References 15 publications

An Energy-Efficient Routing Protocol for a Modified Fat-Tree Topology in System-on-Chip Design

An Energy-Efficient Routing Protocol for a Modified Fat-Tree Topology in System-on-Chip Design

An Overview of Cycle-Accurate, Event-Driven and Full Systems Simulators for Chip-Multiprocessors

Towards Multi-objective Optimization of Automatic Design Space Exploration for Computer Architecture through Hyper-heuristic

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