Approximate Algorithms for Identifying Minima on Min-Sum LDPC Decoders and Their Hardware Implementation

Abstract

This paper introduces algorithms and the corresponding circuits that identify minimum values from among a set of incoming messages. The problem of finding the two minima in a set of messages is approximated by the different problem of finding the minimum of all messages in the set and the second minimum among a subset of the messages. This approximation is here shown to be suitable for hardware LDPC decoders that implement the Min-Sum decoding algorithm and its variations. The introduced approximation simplifies the operation performed in the check-node processor and leads to hardware reduction. The proposed schemes outperform other state-of-the-art simplified MS architectures, approaching the error-corrective performance of the NMS decoding algorithm.

Reduced‐Complexity LDPC Decoding for Next‐Generation IoT Networks

“…The standard IEEE802.16e LDPC codes with code rates 0.5 and 0.75 having a block length of 2304 are used for evaluating the performance of the proposed and some other existing algorithms. The performance of the proposed approach is compared with the NMS, mfMs, svwMS, and exMin-n [49] algorithms with maximum number of decoding iterations equal to 50. Binary phase-shift keying (BPSK) transmission is assumed over an AWGN channel.…”

“…Besides the single minimum-based algorithms, some efforts have been made to propose architectures which compute the two minima from a set of messages for CNU operation [45][46][47][48][49]. A sorting-based architecture was proposed by Xie et al in [46] for finding two minima, but it suffers from large critical delay.…”

Iterative decoding techniques on digital receivers

“…Several VLSI architectures have been proposed for the implementation of LDPC decoders, suitable for either general codes as proposed for example by Masera et al [93], or for codes that assume a special structure, which can be exploited to achieve complexity reduction, such as the architecture proposed by Mansour and Shanbhag [90]. A class of codes with a special structure, consisting of square sub-block matrices, called quasi-cyclic (QC) LDPC codes, has been proposed by Fossorier [50], to further simplify the implementation of both the encoder [88,89] and the decoder [122].…”

VLSI architectures for error correction in digital communication systems

“…Η βασική λειτουργία που εκτελούν τα επεξεργαστικά στοιχεία που υλοποιούν τους αλγορίθμους Min-Sum είναι ο υπολογισμός των δύο μικρότερων τιμών μεταξύ ενός αριθμού θετικών τιμών εισόδου. Το πρόβλημα της εύρεσης των δύο ελαχίστων σε ένα σύνολο μηνυμάτων προσεγγίζεται, από τα συστήματα αποκωδικοποίησης που προτείνονται σε αυτό το κεφάλαιο, από το διαφορετικό πρόβλημα της εύρεσης του μικρότερου όλων των μηνυμάτων του αρχικού συνόλου τιμών, και του δεύτερου μικρότερου ενός υποσυνόλου των μηνυμάτων [150] [146]. Οι προτεινόμενες προσεγγίσεις απλοποιούν τη λειτουργία του κόμβου ελέγχου και οδηγούν σε μείωση της απαιτούμενης επιφάνειας ολοκλήρωσης, ενώ ταυτόχρονα προσεγγίζουν την απόδοση διόρθωσης σφαλμάτων του αλγορίθμου αποκωδικοποίησης NMS.…”

“…The basic function of processing elements that implement the MS algorithms is the computation of the two smallest values among N positive input values. The problem of finding the two minima in a set of messages is approximated, by the decoding schemes proposed in this chapter, by the different problem of finding the minimum of all messages in the set and the second minimum among a subset of the messages [150] [146]. The introduced approximations simplify the check-node operation and lead to hardware reduction, while approaching the error-correcting performance of the NMS decoding algorithm.…”