Approximate 32-bit floating-point unit design with 53% power-area product reduction

Camus, Vincent; Schlachter, Jérémy; Enz, Christian; Gautschi, Michael; Gürkaynak, Frank K.

doi:10.1109/esscirc.2016.7598342

Cited by 35 publications

(18 citation statements)

References 8 publications

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“…Hence, more efforts should be dedicated on reducing the hardware complexity and power consumption of the DSP system to deal with embedding constraints. This goal can be pursued by using specific design methods such as approximate computing techniques [36,37,38]. Exploiting inexact arithmetic circuits for SVD implementation would improve the system efficiency by decreasing the power consumption and hardware resources.…”

Section: Classification Study Based On Fpga Implementationmentioning

confidence: 99%

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Real-Time Digital Signal Processing Based on FPGAs for Electronic Skin Implementation †

Ibrahim

Gastaldo

Chiblé

et al. 2017

Sensors

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Enabling touch-sensing capability would help appliances understand interaction behaviors with their surroundings. Many recent studies are focusing on the development of electronic skin because of its necessity in various application domains, namely autonomous artificial intelligence (e.g., robots), biomedical instrumentation, and replacement prosthetic devices. An essential task of the electronic skin system is to locally process the tactile data and send structured information either to mimic human skin or to respond to the application demands. The electronic skin must be fabricated together with an embedded electronic system which has the role of acquiring the tactile data, processing, and extracting structured information. On the other hand, processing tactile data requires efficient methods to extract meaningful information from raw sensor data. Machine learning represents an effective method for data analysis in many domains: it has recently demonstrated its effectiveness in processing tactile sensor data. In this framework, this paper presents the implementation of digital signal processing based on FPGAs for tactile data processing. It provides the implementation of a tensorial kernel function for a machine learning approach. Implementation results are assessed by highlighting the FPGA resource utilization and power consumption. Results demonstrate the feasibility of the proposed implementation when real-time classification of input touch modalities are targeted.

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Section: Classification Study Based On Fpga Implementationmentioning

confidence: 99%

“…A possible solution would be by using approximate computing which has recently emerged as a promising approach to energy efficient design of digital systems [36]. Approximate computing relies on the ability of many systems and applications to tolerate some loss of quality or optimality in the computed result.…”

Section: Conclusion and Future Perspectivesmentioning

confidence: 99%

Real-Time Digital Signal Processing Based on FPGAs for Electronic Skin Implementation †

Ibrahim

Gastaldo

Chiblé

et al. 2017

Sensors

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“…This technique allows to precisely control mean and maximum errors. It has also shown significant benefits compared or combined with other low-power techniques [25]- [27] or successfully integrated within bigger ASIC systems [28]. In the case of FPGA, the ISA could be particularly interesting in order to overcome FPGA's hardware limitations, e.g.…”

Section: Inexact Speculative Addermentioning

confidence: 99%

Approximate FPGA Implementation of CORDIC for Tactile Data Processing Using Speculative Adders

Franceschi¹,

Camus²,

Ibrahim³

et al. 2017

2017 New Generation of CAS (NGCAS)

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Abstract-In most robotic and biomedical applications, the interest for real-time embedded systems with tactile ability has been growing. For example in prosthetics, a dedicated portable system is needed for developing wearable devices. The main challenges for such systems are low latency, low power consumption and reduced hardware complexity. In order to improve hardware efficiency and reduce power consumption, approximate computing techniques have been assessed. This strategy is suitable for error-tolerant applications involving a large amount of data to be processed, which perfectly fits tactile data processing. This paper presents the first case study of applying Inexact Speculative Adders (ISA) to the FPGA implementation of a Coordinate Rotation Digital Computer (CORDIC) module within the Machine Learning algorithm of a tactile data processing system. The design has been synthesized and implemented on a Xilinx ZYNQ-7000 ZC702 device. Preliminary results have shown dynamic power reduction up to 40 % and delay latency reduction up to 21 % compared to a conventional CORDIC module, at the cost of a negligible average relative error of 0.049 % for sine and 0.003 % for cosine computations.

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“…This provides the designer a wide range of energy-accuracy tradeoffs for arithmetic circuits and more generally for any combinational circuit as demonstrated in [23], [24]. This work however does not address formal verification, which is generally very challenging for any approximate circuit.…”

Section: F Remarksmentioning

confidence: 99%

Design and Applications of Approximate Circuits by Gate-Level Pruning

Schlachter

Camus

Palem

et al. 2017

IEEE Trans. VLSI Syst.

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Abstract-Energy-efficiency is a critical concern for many systems, ranging from IoT objects and mobile devices to highperformance computers. Moreover, after 40 years of prosperity, Moore's law is starting to show its economic and technical limits. Noticing that many circuits are over-engineered and that many applications are error-resilient or require less precision than offered by the existing hardware, approximate computing has emerged as a potential solution to pursue improvements of digital circuits. In this regard, a technique to systematically trade off accuracy in exchange for area, power and delay savings in digital circuits is proposed: Gate-Level Pruning. A CAD tool is build and integrated into a standard digital flow to offer a wide range of costs-accuracy tradeoffs for any conventional design. The methodology is first demonstrated on adders, achieving up to 78 % energy-delay-area reduction for 10 % mean relative error. It is then detailed how this methodology can be applied on a more complex system composed of a multitude of arithmetic blocks and memory: the Discrete Cosine Transform (DCT), which is a key building block for image and video processing applications. Even though arithmetic circuits represent less than 4 % of the entire DCT area, it is shown that the Gate-Level Pruning technique can lead to 21 % energy-delay-area savings over the entire system for a reasonable image quality loss of 24 dB. This significant saving is achieved thanks to the pruned arithmetic circuits which sets some nodes at constant values, enabling the synthesis tool to further simplify the circuit and memory.

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Approximate 32-bit floating-point unit design with 53% power-area product reduction

Cited by 35 publications

References 8 publications

Real-Time Digital Signal Processing Based on FPGAs for Electronic Skin Implementation †

Real-Time Digital Signal Processing Based on FPGAs for Electronic Skin Implementation †

Approximate FPGA Implementation of CORDIC for Tactile Data Processing Using Speculative Adders

Design and Applications of Approximate Circuits by Gate-Level Pruning

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