Approach for a unified functional verification flow

Hany, Amr; Ismail, Ahmed; Kamal, Ahmed H.; Badran, Mohamed

doi:10.1109/siecpc.2013.6550753

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Cited by 3 publications

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“…Ref. [19,20] combine techniques of simulation and formal verification to reach a compromise between confidence and complexity.…”

Section: Literature Surveymentioning

confidence: 99%

SW-VHDL Co-Verification Environment Using Open Source Tools

2020

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The verification of complex digital designs often involves the use of expensive simulators. The present paper proposes an approach to verify a specific family of complex hardware/software systems, whose hardware part, running on an FPGA, communicates with a software counterpart executed on an external processor, such as a user/operator software running on an external PC. The hardware is described in VHDL and the software may be described in any computer language that can be interpreted or compiled into a (Linux) executable file. The presented approach uses open source tools, avoiding expensive license costs and usage restrictions.

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“…Ref. [19,20] combine techniques of simulation and formal verification to reach a compromise between confidence and complexity.…”

Section: Literature Surveymentioning

confidence: 99%