Applying Genetic Parallel Programming to Synthesize Combinational Logic Circuits

Cheang, Sin Man; Lee, Kin Hong; Leung, Kwong Sak

doi:10.1109/tevc.2006.884044

Cited by 19 publications

(12 citation statements)

References 62 publications

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“…It is about 24% of the 19,200 slices available in the Virtex xcv2000E FPGA. In order to compare the qualities of the 3-bit multipliers evolved by the SAMRC running on VRA processor, the best results of CGP [3], GPP+MLP [1], and multiobjective evolutionary design scheme [4] are also listed in Table I. Our best results are in fact as good as the most efficient 3-bit multipliers evolved by other researchers.…”

Section: Resultsmentioning

confidence: 97%

“…This process doesn't rely on the designer's knowledge and experiences. In the contemporary literature, both extrinsic EHW and intrinsic EHW have been employed to synthesize electronic circuits [1,2,3,4,5,6]. As a feasible and efficient approach to intrinsic EHW, virtual reconfiguration technique has been introduced by several researchers [2,6].…”

Section: The Proposed Vra Processormentioning

confidence: 99%

“…As an alternative to conventional specification-based circuit design methods, evolvable hardware (EHW) has been introduced as a methodology for the design automation of combinational logic circuits [1,2,3,4,5]. In this paper, we present a virtual reconfigurable architecture (VRA)-based intrinsic evolvable system to synthesize combinational logic circuits at gate level.…”

Section: Introductionmentioning

confidence: 99%

“…In evolutionary design of combinational logic circuits, most researchers [1,2,3] define the mutation rate parameters as constants for simplicity reason. However, to attain better system performance, the mutation rates are generally required to be optimized as the evolutionary algorithm (EA) progresses [4,5,6].…”

Section: Introductionmentioning

confidence: 99%

“…We perform the experiments on evolving 3-bit multipliers which is generally employed as a benchmark problem by the EHW community [1,2,3,4]. Experimental results show that the VRA processor can automatically synthesize logic circuits.…”

Section: Introductionmentioning

confidence: 99%

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Evolutionary design of combinational logic circuits using VRA processor

Wang

Lee

2009

IEICE Electron. Express

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This paper presents a virtual reconfigurable architecture (VRA)-based evolvable hardware for automatic synthesis of combinational logic circuits. The VRA processor is implemented on a Xilinx FPGA and works through two-stage evolutions: (1) finding a functional circuit, and (2) minimizing the number of gates used. To optimize the algorithm performance in the evolutionary process, a self-adaptive mutation rate control scheme is introduced. The efficiency of the proposed methodology is tested with the evolution of a 3-bit multiplier. The obtained results demonstrate that our approach improves the evolutionary design of electronic circuits in terms of quality of the evolved circuit as well as the computational effort. Keywords: evolvable hardware, self-adaptive mutation rate control, two-stage evolution, VRA Classification: Integrated circuits References[1] S. M. Cheang, K. H. Lee, and K. S. Leung, "Applying genetic parallel programming to synthesize combinational logic circuits," IEEE Trans. Evol. Comput., vol. 11, no. 4, pp. 503-520, Aug. 2007. [2] L. Sekanina and S. Friedl, "An evolvable combinational unit for FPGAs,"J. Computing and Informatics, vol. 23, no. 5, pp. 461-486, 2004.

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Section: Resultsmentioning

confidence: 97%

Section: The Proposed Vra Processormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Evolutionary design of combinational logic circuits using VRA processor

Wang

Lee

2009

IEICE Electron. Express

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A review of bioinspired computer‐aided design tools for hardware design

Lanchares¹,

Garnica²,

Fernández-de-Vega

et al. 2013

Concurrency and Computation

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During the last two decades, bioinspired techniques have emerged as a powerful optimization and problem solving tool for a wide range of real world applications. Parallel architectures and computer-aided design tools have been also influenced by this evolutionary fashion. In this paper, we give a broader view of the application of techniques inspired by nature to hardware design and parallel architectures problem solving. Our aim is to furnish an overview of the various bioinspired techniques based tools that have been used so far to solve the problems of automatic hardware design. We can claim that a lot of the approaches found in the literature suffer from a lack of interdisciplinary interaction among researchers of both evolutionary computation and hardware design fields. In addition, we have also detected that some multi-objective problems do not use the appropriate algorithms.Among widely known heuristics, gradient algorithms, such as Hill Climbing, were soon employed. These algorithms start the search process from a single point, stochastically generated from the solution space, and then perform a search process using the direction of the gradient towards the objective function. These algorithms are of an easy implementation and relatively efficient. However, local optima are usually the output and no general procedures exist to know the distance from the global optimum.An improvement over the previous approach was obtained by the simulated annealing (SA) algorithm [2], capable of removing some of the previously described disadvantages. SA begins with a randomly generated candidate solution-a point in the search space-with some specific features, and then, the algorithm proceeds by applying a disturbance to the candidate solution, thus trying to improve it. If the solution improves, it is selected and becomes the next candidate solution; otherwise, a probability decides whether to continue with the initial candidate or with the new one. The probability of accepting a worse solution depends on the system temperature-a fundamental parameter for SA. The system starts with a very high temperature, so most of the worse solutions are accepted at the beginning. The temperature is then lowered gradually; the lower the temperature, the lower the probability of accepting a worse solution. So far, SA has been the most frequently employed heuristic in computer-aided design (CAD) tools.Nevertheless, a new kind of heuristic has gained popularity: bioinspired algorithms (BAs) [3]. Among BAs, evolutionary algorithms (EAs) try to emulate the natural evolution of species, following Darwin's principles of natural selection. One of their main advantages is the employment of a set (population) of candidate solutions (individuals) at the same time, which gives rise to an intrinsically parallel search process. We can also find other bioinspired approaches on the basis of the social behavior of the species such as particle swarm optimization (PSO) [4] or ant colony optimization (ACO) [5] algorithms.This review focuses on the appli...

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Genetic Programming

2010

Decision Engineering

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Applying Genetic Parallel Programming to Synthesize Combinational Logic Circuits

Cited by 19 publications

References 62 publications

Evolutionary design of combinational logic circuits using VRA processor

Evolutionary design of combinational logic circuits using VRA processor

A review of bioinspired computer‐aided design tools for hardware design

Genetic Programming

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