Applications of a four-quadrant multiplier

A high speed analog VLSI image acquisition and low-level image processing system is presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Each pixel include a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a fourquadrant multiplier architecture. A 64 9 64 pixel proof-ofconcept chip was fabricated in a 0.35 lm standard CMOS process, with a pixel size of 35 lm 9 35 lm. The chip can capture raw images up to 10,000 fps and runs low-level image processing at a framerate of 2,000-5,000 fps.

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“…This unit is based on four-quadrant analog multipliers [36,37] named M1, M2, M3, and M4, as illustrated in Fig. 4.…”

Section: Analog Arithmetic Unit (A 2 U)mentioning

confidence: 99%

A high speed programmable focal-plane SIMD vision chip

Ginhac

Dubois

Heyrman

et al. 2009

Analog Integr Circ Sig Process

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“…To that end, we designed an analog arithmetic unit (A 2 U) which is able to perform convolution of the pixels with a 2x2 dynamic kernel. This unit is based on four-quadrant analog multipliers [42], [43] named M1, M2, M3, and M4, as illustrated in Fig. 5.…”

Section: B Analog Memory Amplifier and Multiplexer : [Am]mentioning

confidence: 99%

An SIMD Programmable Vision Chip with High-Speed Focal Plane Image Processing

Ginhac¹,

Dubois²,

Paindavoine³

et al. 2009

J Embedded Systems

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A high speed analog VLSI image acquisition and low-level image processing system is presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel operators are implemented on the circuit. Each pixel include a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A 64 × 64 pixel proofof-concept chip was fabricated in a 0.35 µm standard CMOS process, with a pixel size of 35 µm × 35 µm. A dedicated embedded platform including FPGA and ADCs has also been designed to evaluate the vision chip. The chip can capture raw images up to 10 000 frames per second and runs low-level image processing at a framerate of 2 000 to 5 000 frames per second.

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“…In this way, the local derivative in the direction of vector is continuously computed as a linear combination of two basis functions, the derivatives in the and directions. Using a four-quadrant multiplier [30], [31] (see Section IV-C for details of design and implementation), the product of the derivatives by a cosine function can easily be computed. The output product , as shown in Fig.…”

Section: A Spatial Gradientsmentioning

confidence: 99%