An SIMD Programmable Vision Chip with High-Speed Focal Plane Image Processing

Abstract

A high speed analog VLSI image acquisition and low-level image processing system is presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel operators are implemented on the circuit. Each pixel include a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A 64 × 64 pixel proofof-concept chip was fabricated in a 0.35 µm standard CMOS process, with a pixel size of 35 µm × 35 µm. A dedicated embedded platform including FPGA and ADCs has also been designed to evaluate the vision chip. The chip can capture raw images up to 10 000 frames per second and runs low-level image processing at a framerate of 2 000 to 5 000 frames per second.

In‐pixel analog memories for a pixel‐based background subtraction algorithm on CMOS vision sensors

“…Obtained values show good performance if compared with Ginhac et al 25 (4% in 20 ms) or with Carey et al 26 (5% in 1 s). However, our results come from electrical simulations whereas Ginhac et al 25 and Carey et al 26 report measurements from fabricated chips. Also, no information is given about how these data were extracted and if the measurement process could affect the results.…”

Mixed signal SIMD cellular processor array vision chip operating at 30,000 fps

“…Registers decayed at a worst-case rate of 5% of full-scale range per second (cf. 4% over 20ms in [4]). Over a typical frame interval of 50ms, this decay rate has a negligible effect.…”

“…Many vision chips, in common with the chip described here, operate as SIMD computational devices. Such devices have been presented widely [1][2][3][4][5][6][7][8] in both digital, analogue and mixed signal form.…”

Smart cameras on a chip: Using complementary metal-oxide-semiconductor (CMOS) image sensors to create smart vision chips

“…A fundamental tradeoff must be made between three dependent and correlated variables: pixel size, processing element area, and fill-factor. This implies various points of view (Ginhac et al, 2008):…”