Application-specific topology generation algorithms for network-on-chip design

Abstract

Network-on-chip (NoC) is an alternative approach to traditional communication methods for system-on-chip architectures. Irregular topologies are preferable for the application specific NoC designs as they offer huge optimisation space in contrast to their regular counterparts. Generating an application-specific topology as part of the synthesis flow of a NoC architecture is a challenging problem as there may be several topology alternatives, each of which may be superior to the others based on the different objective criteria. In this study, the authors tackle at this problem and propose a heuristic and a genetic algorithm-based methods. The heuristic method, called TopGen, is a two-phase application-specific topology generation algorithm aiming to minimise the energy consumption of the system. TopGen first decomposes the given application into clusters based on the communication traffic. It then maps the clusters onto the routers and connects them in such a way that the communication cost of the network is minimised. The second algorithm, called GA-based topology generation algorithm-based topology generation algorithm (GATGA), is based on a genetic algorithm, which initially creates a set of solutions and uses genetic operators to reproduce new topologies from them. The authors compared our algorithms with existing methods through several multimedia benchmarks and custom generated graphs. TopGen and GATGA obtained better results than previous methods with negligible area and link length overheads.

Fault-Tolerant Topology Generation Method for Application-Specific Network-on-Chips

“…Clearly, the generated non-fault-tolerant irregular topology will need at least l min links to connect r min routers, where l min = r min − 1, as proven in [4].…”

“…There are also heuristic-based irregular topology generation algorithms in the literature [4], [8]. These methods first determine the topology connection and then later decide the floorplanning, as opposed to the methods in [9] and [11].…”

“…Although regular topologies are easy to construct and reusable, applications cannot be well optimized on them. Irregular topologies are beneficial for designing application specific NoCs since the design parameters such as energy consumption, performance, and area can be optimized better than their regular counterparts [4]. Several studies have been published regarding energyefficient and/or fault-tolerant regular topology-based NoC designs, especially for mesh topologies [5], [6], [7].…”

“…Application-specific topologies generated by current methods have only one communication path between any communicating nodes [4], [8], [9]. If there is a permanent fault in any of the links or ports as a result of the fabrication process, the system cannot recover its functionality and the chip becomes useless.…”

Fault-Tolerant Irregular Topology Design Method for Network-on-Chips

“…Although regular topologies are easy to construct and reusable, applications cannot be well optimized on them. Irregular topologies are designed to be application specific, which allows optimizing power consumption, performance, and area [2]. Several studies have been published regarding energy-efficient and/or faulttolerant regular topology-based NoC designs, especially for mesh topologies [3].…”