Application Specific Low Latency Instruction Cache for NAND Flash Memory Based Embedded Systems

Lee, Kwangyoon; Orailoğlu, Alex

doi:10.1109/sasp.2008.4570788

Cited by 3 publications

(1 citation statement)

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“…In recent years, many studies for FTL schemes (especially hybrid-level FTL schemes) have been proposed [5], [6], [7], [8], [9], [10], [11]. Although the above FTL schemes provide good solutions in terms of endurance, wear-leveling, memory usage, and response time, none of them have considered to reuse free pages in both data blocks and log blocks in a merge operation.…”

Section: Introductionmentioning

confidence: 99%

An endurance-enhanced Flash Translation Layer via reuse for NAND flash memory storage systems

Wang

Liu

Qin

et al. 2011

2011 Design, Automation &Amp; Test in Europe

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NAND flash memory is widely used in embedded systems due to its non-volatility, shock resistance and high cell density. In recent years, various Flash Translation Layer (FTL) schemes (especially hybrid-level FTL schemes) have been proposed. Although these FTL schemes provide good solutions in terms of endurance and wear-leveling, none of them have considered to reuse free pages in both data blocks and log blocks during a merge operation. By reusing these free pages, less free blocks are needed and the endurance of NAND flash memory is enhanced. We evaluate our reuse strategy using a variety of application specific I/O traces from Windows systems. Experimental results show that the proposed scheme can effectively reduce the erase counts and enhance the endurance of flash memory.

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