Application of high-κ gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology

Chau, R.; Brask, Justin; Datta, Suman; Dewey, G.; Doczy, M.; Doyle, B.S.; Kavalieros, J.; Jin, B.; Metz, M.; Majumdar, Amlan; Radosavljević, M.

doi:10.1016/j.mee.2005.04.035

Cited by 134 publications

(73 citation statements)

References 5 publications

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“…[1][2][3][4][5][6] The motivation for using high mobility channel materials and high-k gate oxides is for lower leakage, lower power consumption, and higher speed of operation for minimum channel lengths below 22 nm. However, there are a range of challenges associated with the integration of high mobility compound semiconductor channels into a MOSFET process, which include the integration of the high mobility materials onto a large area silicon platform, forming high-k gate oxide layers on the III-V substrate, and finding a suitable p channel device when using III-V materials for both the p and n channel MOSFET.…”

Section: Introductionmentioning

confidence: 99%

An investigation of capacitance-voltage hysteresis in metal/high-k/In0.53Ga0.47As metal-oxide-semiconductor capacitors

Lin

Gomeniuk

Monaghan

et al. 2013

Journal of Applied Physics

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In this work, we present the results of an investigation into charge trapping in metal/high-k/In0.53Ga0.47As metal-oxide-semiconductor capacitors (MOS capacitors), which is analysed using the hysteresis exhibited in the capacitance-voltage (C-V) response. The availability of both n and p doped In0.53Ga0.47As epitaxial layers allows the investigation of both hole and electron trapping in the bulk of HfO2 and Al2O3 films formed using atomic layer deposition (ALD). The HfO2/In0.53Ga0.47As and Al2O3/In0.53Ga0.47As MOS capacitors exhibit an almost reversible trapping behaviour, where the density of trapped charge is of a similar level to high-k/In0.53Ga0.47As interface state density, for both electrons and holes in the HfO2 and Al2O3 films. The experimental results demonstrate that the magnitude of the C-V hysteresis increases significantly for samples which have a native oxide layer present between the In0.53Ga0.47As surface and the high-k oxide, suggesting that the charge trapping responsible for the C-V hysteresis is taking place primarily in the interfacial oxide transition layer between the In0.53Ga0.47As and the ALD deposited oxide. Analysis of samples with a range of oxide thickness values also demonstrates that the magnitude of the C-V hysteresis window increases linearly with the increasing oxide thickness, and the corresponding trapped charge density is not a function of the oxide thickness, providing further evidence that the charge trapping is predominantly localised as a line charge and taking place primarily in the interfacial oxide transition layer located between the In0.53Ga0.47As and the high-k oxide. (C) 2013 AIP Publishing LLC

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Section: Introductionmentioning

confidence: 99%

An investigation of capacitance-voltage hysteresis in metal/high-k/In0.53Ga0.47As metal-oxide-semiconductor capacitors

Lin

Gomeniuk

Monaghan

et al. 2013

Journal of Applied Physics

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“…Consequently, the thinness of the oxide allows a current that tunnels through the gate towards the channel of a transistor, so much so that in current sub 90 nm technologies, gate leakage can be nearly 1/3 as much as subthreshold leakage [8]. In order to reduce the gate leakage, some manufacturers have resorted to high-k dielectric materials, such as Hafnium, to keep the gate leakage in check [11].…”

Section: Methods Assumptions and Proceduresmentioning

confidence: 99%

Exploration of Nanometer Cognitive Reasoning Very Large Scale Integration (VLSI) Computer Architecures

Stine¹,

James²

2012

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Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. SPONSORING/MONITORING AGENCY NAME(S) AND ADDRESS(ES)Air Force Research Laboratory/RITB 525 Brooks Road Rome NY 13441-4505 SPONSOR/MONITOR'S ACRONYM(S)AFRL/RI SPONSORING/MONITORING AGENCY REPORT NUMBER AFRL-RI-RS-TR-2012-134 DISTRIBUTION AVAILABILITY STATEMENTApproved for Public Release; Distribution Unlimited. PA# 88 ABW-2012-2306 Date Cleared: 16 Apr 2012 SUPPLEMENTARY NOTES ABSTRACTThe objectives of this work were to design, develop, and evaluate support for the design of low-power hardware computer architectures at the Very Large Scale Integration (VLSI) level. The objectives were realized by achieving complete design flow integration with commercial and open-source Electronic Design Automation tools. The design flow takes as inputs a high-level system-level architecture description, along with area, critical path delay, and power dissipation constraints. Based on the System on Chip architecture description and design constraints, the tools automatically generate synthesizable Hardware Descriptive Language (HDL) models, embedded memories, and custom components to implement the specified VLSI architecture. Simulation results showed significant improvement over previous approaches with respect to power dissipation and leakage reduction.

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“…It is becoming clear that scaling of CMOS can only be realized by the continuous introduction of new materials (high-κ /metal gates, 43 SiGe-SiC, 44 Ge…”

Section: Contact Materials To Ge and Iii-v Compoundsmentioning

confidence: 99%

Contact materials for nanoelectronics

Alshareef¹,

Quevedo‐Lopez²,

Majhi³

2011

MRS Bull.

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Application of high-κ gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology

Cited by 134 publications

References 5 publications

An investigation of capacitance-voltage hysteresis in metal/high-k/In0.53Ga0.47As metal-oxide-semiconductor capacitors

An investigation of capacitance-voltage hysteresis in metal/high-k/In0.53Ga0.47As metal-oxide-semiconductor capacitors

Exploration of Nanometer Cognitive Reasoning Very Large Scale Integration (VLSI) Computer Architecures

Contact materials for nanoelectronics

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